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| publication# 19436 rev. a amendment /+1 issue date: april 1995 this document contains information on a product under development at advanced micro devices, inc. the information is intended to help you to evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice. advanced micro devices AM79C970A pcnet tm -pci ii single-chip full-duplex ethernet controller for pci local bus product preliminary
distinctive characteristics single-chip ethernet controller for the periph- eral component interconnect (pci) local bus supports iso 8802-3 (ieee/ansi 802.3) and ethernet standards direct interface to the pci local bus (revision 2.0 compliant) high-performance 32-bit bus master architec- ture with integrated dma buffer management unit for low cpu and bus utilization software compatible with amd pcnet family, lance/c-lance, and am79c900 ilacc regis- ter and descriptor architecture compatible with pcnet family driver software full-duplex operation for increased network bandwidth big endian and little endian byte alignments supported 3.3 v/5 v signaling for pci bus interface low-power cmos design with two sleep modes allows reduced power consumption for critical battery powered applications and green pcs integrated magic packet tm support for remote wake up of green pcs individual 272-byte transmit and 256-byte re- ceive fifos provide frame buffering for in- creased system latency and support the following features: automatic retransmission with no fifo reload automatic receive stripping and transmit pad- ding (individually programmable) automatic runt frame rejection automatic selection of received collision frames microwire eeprom interface supports jumperless design and provides through-chip programming supports optional boot prom for diskless node applications look-ahead packet processing (lapp) data handling technique reduces system overhead by allowing protocol analysis to begin before end of receive frame integrated manchester encoder/decoder provides integrated attachment unit interface (aui) and 10base-t transceiver with automatic port selection automatic twisted-pair receive polarity detec- tion and automatic correction of the receive polarity optional byte padding to long-word boundary on receive dynamic transmit fcs generation programma- ble on a frame-by-frame basis internal/external loopback capabilities supports the following types of network inter- faces: aui to external 10base2, 10base5, 10base-t or 10base-f mau internal 10base-t transceiver with smart squelch to twisted-pair medium jtag boundary scan (ieee 1149.1) test access port interface and nand tree test mode for board-level production connectivity test supports lance general purpose serial inter- face (gpsi) supports external address detection interface (eadi) 4 programmable leds for status indication 132-pin pqfp package general description the 32-bit pcnet-pci ii single-chip full-duplex ethernet controller is a highly integrated ethernet system solution designed to address high-performance system applica- tion requirements. it is a flexible bus-mastering device that can be used in any application, including network- ready pcs, printers, fax modems, and bridge/router de- signs. the bus-master architecture provides high data throughput in the system and low cpu and system bus utilization. the pcnet-pci ii controller is fabricated with amd's advanced low-power cmos process to provide low operating and standby current for power sensitive applications.
amd p r e l i m i n a r y 2 AM79C970A the pcnet pci ii controller is a complete ethernet node integrated into a single vlsi device. it contains a bus interface unit, a dma buffer management unit, an ieee 802.3 compliant media access control (mac) function, individual 272 byte transmit and 256 byte receive fifos, an ieee 802.3 compliant attachment unit interface (aui) and twisted pair transceiver media attachment unit (10base t mau) that can both operate in either half duplex or full duplex mode. the pcnet pci ii controller is register compatible with the lance (am7990) ethernet controller, the c lance (am79c90) ethernet controller, the ilacc (am79c900) ethernet controller, and all ethernet controllers in the pcnet family, including the pcnet isa controller (am79c960), pcnet isa+ controller (am79c961), pcnet isa ii controller (am79c961a), pcnet 32 controller (am79c965), pcnet pci controller (am79970), and the pcnet scsi controller (am79c974). the buffer management unit supports the c lance, ilacc, and pcnet descriptor software models. the pcnet pci ii controller is software compatible with the novell ne2100 and ne1500 ethernet adapter card architectures. the 32 bit multiplexed bus interface unit provides a di rect interface to pci local bus applications, simplifying the design of an ethernet node in a pc system. the pcnet pci ii controller provides the complete interface to an expansion rom, allowing add on card designs with only a single load per pci bus interface pin. with its built in support for both little and big endian byte align ment, this controller also addresses proprietary non pc applications. the pcnet pci ii controller's advanced cmos design allows the bus interface to be connected to either a 5 v or a 3.3 v signaling environ ment. both nand tree and jtag test interfaces are provided. the pcnet pci ii controller supports automatic configuration in the pci configuration space. additional pcnet pci ii configuration parameters, including the unique ieee physical address, can be read from an ex ternal non volatile memory (microwire eeprom) im mediately following system reset. the controller has the capability to automatically select either the aui port or the twisted pair transceiver. only one interface is active at any one time. both network in terfaces can be programmed to operate in either half duplex or full duplex mode. the individual transmit and receive fifos optimize system overhead, providing suf ficient latency during frame transmission and reception, and minimizing intervention during normal network error recovery. the integrated manchester encoder/decoder (mendec) eliminates the need for an external serial in terface adapter (sia) in the system. the built in general purpose serial interface (gpsi) allows the mendec to be by passed. in addition, the device provides programmable on chip led drivers for trans mit, receive, collision, receive polarity, link integrity, ac tivity, or jabber status. the pcnet pci ii controller also provides an external address detection interface (eadi) to allow fast external hardware address filtering in internetworking applications. for power sensitive applications where low stand by current is desired, the device incorporates two sleep functions to reduce over all system power consumption, excellent for notebooks and green pcs. in conjunction with these low power modes, the pcnet pci ii controller also has integrated functions to support magic packet, an inexpensive technology that allows remote wake up of green pcs. p r e l i m i n a r y amd 3 AM79C970A block diagram 19436a 1 fifo control pci bus interface unit rcv fifo xmt fifo clk par frame c/ be [3:0] trdy irdy lock idsel devsel req gnt perr serr inta stop ad[31:00] rst nout xtal1 xtal2 sleep txen txclk txdat rxen rxclk rxdat clsn gpsi port jtag port control srdclk srd ear eadi port sf/bd txd+/- txp+/- rxd+/- lnkst 10base-t mau do+/- di +/- ci+/- manchester encoder/ decoder (pls) & aui port dxcvr 802.3 mac core era[7:0] erd[7:0] eraclk eroe expansion rom interface led1 led2 led3 led control eecs eesk eedi eedo microwire eeprom interface tck tms tdo tdi buffer management unit amd p r e l i m i n a r y 4 AM79C970A table of contents distinctive characteristics 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . general description 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . block diagram 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . related products 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . connection diagram 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin designations 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . listed by pin number 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . listed by group 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . listed by driver type 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin description 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pci interface 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . board interface 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . microwire eeprom interface 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . expansion rom interface 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . attachment unit interface 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . twisted pair interface 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . general purpose serial interface 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . external address detection interface 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ieee 1149.1 test access port interface 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . test interface 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power supply pins 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . basic functions 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . system bus interface function 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . software interface 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . network interfaces 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . detailed functions 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . slave bus interface unit 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . slave configuration transfers 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . slave i/o transfers 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . expansion rom transfers 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . exclusive access 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . slave cycle termination 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . disconnect when busy 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . disconnect of burst transfer 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . disconnect when locked 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . parity error response 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . master bus interface unit 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bus acquisition 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bus master dma transfers 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . basic non burst read transfer 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . basic burst read transfer 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . basic non burst write transfer 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . basic burst write transfer 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . target initiated termination 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . disconnect with data transfer 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . disconnect without data transfer 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . target abort 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p r e l i m i n a r y amd 5 AM79C970A master initiated termination 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . preemption during non burst transaction 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . preemption during burst transaction 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . master abort 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . parity error response 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . advanced parity error handling 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . initialization block dma transfers 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . descriptor dma transfers 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . fifo dma transfers 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . non burst fifo dma transfers 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . burst fifo dma transfers 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . buffer management unit 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . initialization 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . re initialization 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . suspend 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . buffer management 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . descriptor rings 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . polling 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . transmit descriptor table entry 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . receive descriptor table entry 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . media access control 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . transmit and receive message data encapsulation 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . framing 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . destination address handling 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . error detection 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . media access management 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . medium allocation 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . collision handling 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . transmit operation 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . transmit function programming 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . automatic pad generation 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . transmit fcs generation 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . transmit exception conditions 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . loss of carrier 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . late collision 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sqe test error 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . receive operation 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . receive function programming 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address matching 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . automatic pad stripping 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . receive fcs checking 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . receive exception conditions 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . loopback operation 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gpsi loopback modes 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . aui loopback modes 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t mau loopback modes 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . miscellaneous loopback features 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . magic packet mode 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . manchester encoder/decoder 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . external crystal characteristics 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . external clock drive characteristics 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mendec transmit path 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . transmitter timing and operation 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . receiver path 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input signal conditioning 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . amd p r e l i m i n a r y 6 AM79C970A clock acquisition 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pll tracking 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . carrier tracking and end of message 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . data decoding 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . jitter tolerance definition 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . attachment unit interface 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . differential input termination 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . collision detection 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . twisted pair transceiver 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . twisted pair transmit function 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . twisted pair receive function 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . link test function 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . polarity detection and reversal 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . twisted pair interface status 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . collision detection function 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . signal quality error test function 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . jabber function 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power down 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10base t interface connection 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . full duplex operation 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . full duplex link status led support 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . general purpose serial interface 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . external address detection interface 84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . expansion rom interface 85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eeprom microwire interface 88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . automatic eeprom read operation 88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eeprom auto detection 88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . direct access to the microwire interface 89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eeprom programmable registers 89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eeprom map 90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . led support 90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power savings modes 92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ieee 1149.1 test access port interface 92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . boundary scan circuit 92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tap finite state machine 92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supported instructions 92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . instruction register and decoding logic 93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . boundary scan register 93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . other data registers 93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . nand tree testing 94 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reset 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . h_reset 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . s_reset 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . stop 97 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . software access 97 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pci configuration registers 97 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i/o resources 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i/o registers 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address prom space 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reset register 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . word i/o mode 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . double word i/o mode 99 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . user accessible registers 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pci configuration registers 101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p r e l i m i n a r y amd 7 AM79C970A pci vendor id 101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pci device id register 101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pci command register 102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pci status register 103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pci revision id register 104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pci programming interface register 104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pci sub class register 104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pci base class register 104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pci latency timer register 104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pci header type register 104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pci i/o base address register 105 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pci memory mapped i/o base address register 105 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pci expansion rom base address register 106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pci interrupt line register 106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pci interrupt pin register 106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pci min_gnt register 107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pci max_lat register 107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rap register 107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rap: register address port 107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . control and status registers 107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr0: pcnet pci ii controller controller status register 107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr1: initialization block address 0 110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr2: initialization block address 1 110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr3: interrupt masks and deferral control 111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr4: test and features control 113 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr5: extended control and interrupt 115 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr6: rx/tx descriptor table length 117 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr8: logical address filter 0 117 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr9: logical address filter 1 118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr10: logical address filter 2 118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr11: logical address filter 3 118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr12: physical address register 0 118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr13: physical address register 1 118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr14: physical address register 2 118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr15: mode 119 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr16: initialization block address lower 121 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr17: initialization block address upper 121 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr18: current receive buffer address lower 121 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr19: current receive buffer address upper 121 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr20: current transmit buffer address lower 122 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr21: current transmit buffer address upper 122 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr22: next receive buffer address lower 122 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr23: next receive buffer address upper 122 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr24: base address of receive descriptor ring lower 122 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr25: base address of receive descriptor ring upper 122 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr26: next receive descriptor address lower 123 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr27: next receive descriptor address upper 123 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr28: current receive descriptor address lower 123 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr29: current receive descriptor address upper 123 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr30: base address of transmit descriptor ring lower 123 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr31: base address of transmit descriptor ring upper 123 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr32: next transmit descriptor address lower 123 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr33: next transmit descriptor address upper 124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr34: current transmit descriptor address lower 124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr35: current transmit descriptor address upper 124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . amd p r e l i m i n a r y 8 AM79C970A csr36: next next receive descriptor address lower 124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr37: next next receive descriptor address upper 124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr38: next next transmit descriptor address lower 124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr39: next next transmit descriptor address upper 124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr40: current receive byte count 125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr41: current receive status 125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr42: current transmit byte count 125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr44: next receive byte count 125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr45: next receive status 125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr46: poll time counter 125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr47: polling interval 126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr58: software style 126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr60: previous transmit descriptor address lower 128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr61: previous transmit descriptor address upper 128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr62: previous transmit byte count 128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr63: previous transmit status 128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr64: next transmit buffer address lower 129 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr65: next transmit buffer address upper 129 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr66: next transmit byte count 129 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr67: next transmit status 129 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr72: receive descriptor ring counter 129 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr74: transmit descriptor ring counter 129 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr76: receive descriptor ring length 130 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr78: transmit descriptor ring length 130 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr80: dma transfer counter and fifo watermark control 130 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr82: bus activity timer 132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr84: dma address register lower 132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr85: dma address register upper 132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr86: buffer byte counter 132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr88: chip id register lower 133 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr89: chip id register upper 133 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr94: transmit time domain reflectometry count 133 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr100: bus timeout 133 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr112: missed frame count 134 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr114: receive collision count 134 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr122: advanced feature control 134 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . csr124: test register 1 134 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bus configuration registers 135 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bcr0: master mode read active 136 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bcr1: master mode write active 136 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bcr2: miscellaneous configuration 136 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bcr4: link status led (lnkst) 139 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bcr5: led1 status 141 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bcr6: led2 status 143 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bcr7: led3 status 145 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bcr9: full duplex control 147 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bcr16: i/o base address lower 147 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bcr16: i/o base address upper 147 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bcr18: burst and bus control register 148 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bcr19: eeprom control and status 149 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bcr20: software style 152 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bcr21: interrupt control 154 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bcr22: pci latency register 154 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . initialization block 154 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rlen and tlen 155 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p r e l i m i n a r y amd 9 AM79C970A rdra and tdra 156 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ladrf 156 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . padr 157 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mode 157 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . receive descriptors 157 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rmd0 158 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rmd1 158 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rmd2 159 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rmd3 160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . transmit descriptors 160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tmd0 161 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tmd1 161 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tmd2 162 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tmd3 163 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . register summary 164 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pci configuration registers 164 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . control and status registers 165 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bus configuration registers 168 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum rating 169 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating ranges 169 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dc characteristics 169 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . switching characteristics 172 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bus interface 172 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10base t interface 174 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . aui 175 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gpsi 176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eadi 177 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . key to switching waveforms 178 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . switching test circuits 178 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . switching waveforms 180 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . system bus interface 180 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10base t interface 184 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . aui 186 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gpsi 189 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . eadi 190 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . physical dimensions 191 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . appendix a: pcnet pci ii compatible media interface modules a 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10base t filters and transformers a 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . aui isolation transformers a 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dc/dc converters a 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . manufacturer contact information a 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . appendix b: recommendation for power and ground decoupling b 1 . . . . . . . . . . . . . . . . . . . . . . . . . appendix c: alternative method for initialization c 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . appendix d: look ahead packet processing concept d 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . introduction of the lapp concept d 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . outline of the lapp flow d 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lapp software requirements d 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . amd p r e l i m i n a r y 10 AM79C970A lapp rules for parsing of descriptors d 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . some examples of lapp descriptor interaction d 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . buffer size tuning d 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . an alternative lapp flow the two interrupt method d 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . appendix e: pcnet pci ii and pcnet pci differences e 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . overview e 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . new features e 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . list of register bit changes e 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pci configuration space e 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . control and status registers e 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bus configuration registers e 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . receive descriptor e 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . transmit descriptor e 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . list of pin changes e 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p r e l i m i n a r y amd 11 AM79C970A related products part no. description am79c90 cmos local area network controller for ethernet (c lance) am7996 ieee 802.3/ethernet/cheapernet tap transceiver am79c98 twisted pair ethernet transceiver (tpex) am79c100 twisted pair ethernet transceiver plus (tpex+) am79c900 integrated local area communications controller (ilacc ) am79c940 media access controller for ethernet (mace tm ) am79c960 pcnet isa single chip ethernet controller (for isa bus) am79c961 pcnet isa+ single chip ethernet controller (with microsoft plug n' play support) am79c961a pcnet isa ii single chip full duplex ethernet controller (with microsoft plug n' play support) am79c965 pcnet 32 single chip 32 bit ethernet controller (for 486 and vl buses) am79c970 pcnet pci ii single chip ethernet controller for pci local bus am79c974 pcnet scsi combination ethernet and scsi controller for pci systems am79c981 integrated multiport repeater plus tm (imr+ tm ) am79c987 hardware implemented management information base tm (himib tm ) amd p r e l i m i n a r y 12 AM79C970A connection diagram - 132 pin pqfp ad28 ad29 vssb ad30 ad31 tdo req vss tms gnt vdd clk rst vss tck inta reserved sleep eecs vss eesk/ led1 /sfbd eedi/ lnkst eedo/ led3 /srd vdd avdd2 ci+ ci- di+ di- avdd1 do+ do- avss1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 132 131 130 129 128 127 126 125 124 123 122 121 120 11 9 11 8 11 7 11 6 11 5 11 4 11 3 11 2 111 11 0 109 108 107 106 105 104 103 102 101 100 vddb ad27 ad26 vssb ad25 ad24 c/ be3 vdd tdi idsel vss ad23 ad22 vssb ad21 ad20 vddb ad19 ad18 vssb ad17 ad16 c/ be2 frame irdy trdy devsel stop lock vss perr serr vddb xtal2 avss2 xtal1 avdd3 txd+ txp+ txd- txp- avdd4 rxd+ rxd- vss led2 /srdclk erd0/rxdat erd1/rxclk vdd erd2/rxen vss erd3/clsn erd4/txclk vss erd5 erd6/txen vdd erd7/txdat era0 era1 vss era2 era3 era4 era5 vss pa r c/ be1 ad15 vssb ad14 ad13 ad12 ad11 ad10 vssb ad9 ad8 vddb c/ be0 ad7 ad6 vssb ad5 ad4 ad3 ad2 vssb ad1 ad0 ear vdd eroe vss dxcvr/nout vss eraclk era7 era6 AM79C970A pcnet-pci ii pin 1 is marked for orientation reserved = don't connect 19436a 2 pin 1 is marked for orientation. reserved = don't connect p r e l i m i n a r y amd 13 AM79C970A connection diagram - 144 pin tqfp 19436a 3 pin 1 is marked for orientation. reserved = don't connect 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 nc vddb ad27 ad26 vssb ad25 ad24 c/ be3 vdd tdi idsel vssb ad23 ad22 vssb ad21 ad20 vddb ad19 ad18 vssb ad17 ad16 c/ be2 frame irdy trdy devsel stop lock vss perr serr vddb nc nc nc nc xtal2 avss2 xtal1 avdd3 txd+ txp+ txd- txp- avdd4 rxd+ rxd- vss led2 /srdclk erd0/rxdat erd1/rxclk vdd erd2/rxen vss erd3/clsn erd4/txclk vss erd5 erd6/txen vdd erd7/txdat era0 era1 vss era2 era3 era4 era5 vss nc nc par c/ be1 ad15 vssb ad14 ad13 ad12 ad11 ad10 vssb ad9 ad8 vddb c/ be0 ad7 ad6 vssb ad5 ad4 ad3 ad2 vssb ad1 ad0 ear vdd eroe vss dxcvr/nout vss eraclk era7 era6 nc nc nc nc ad28 ad29 vssb ad30 ad31 tdo req vss tms gnt vdd clk rst vss tck inta reserved sleep eecs vss eesk/ led1 /sfbd eedi/ lnkst eed0/ led3 /srd vdd avdd2 ci+ ci- di+ di- avdd1 do+ di- avss1 nc pcnet-pci ii AM79C970Avc amd p r e l i m i n a r y 14 AM79C970A pin designations - 132 pin pqfp listed by pin number pin no. name pin no. name pin no. name pin no. name 1 v ddb 34 par 67 v ss 100 avss1 2 ad27 35 c/ be 1 68 era5 101 do- 3 ad26 36 ad15 69 era4 102 do+ 4 v ssb 37 v ssb 70 era3 103 avdd1 5 ad25 38 ad14 71 era2 104 di 6 ad24 39 ad13 72 v ss 105 di+ 7 c/ be 3 40 ad12 73 era1 106 ci- 8 v dd 41 ad11 74 era0 107 ci+ 9 tdi 42 ad10 75 erd7/txdat 108 avdd2 10 idsel 43 v ssb 76 v dd 109 v dd 11 v ss 44 ad9 77 erd6/txen 110 eedo/ led3 /srd 12 ad23 45 ad8 78 erd5 111 eedi/ lnkst 13 ad22 46 v ddb 79 v ss 112 eesk/ led1 /sfbd 14 v ssb 47 c/ be 0 80 erd4/txclk 113 v ss 15 ad21 48 ad7 81 erd3/clsn 114 eecs 16 ad20 49 ad6 82 v ss 115 sleep 17 v ddb 50 v ssb 83 erd2/rxen 116 reserved 18 ad19 51 ad5 84 v dd 117 inta 19 ad18 52 ad4 85 erd1/rxclk 118 tck 20 v ssb 53 ad3 86 erd0/rxdat 119 v ss 21 ad17 54 ad2 87 led2 /srdclk 120 rst 22 ad16 55 v ssb 88 v ss 121 clk 23 c/ be 2 56 ad1 89 rxd- 122 v dd 24 frame 57 ad0 90 rxd+ 123 gnt 25 irdy 58 ear 91 avdd4 124 tms 26 trdy 59 v dd 92 txp 125 v ss 27 devsel 60 eroe 93 txd- 126 req 28 stop 61 v ss 94 txp+ 127 tdo 29 lock 62 dxcvr/nout 95 txd+ 128 ad31 30 v ss 63 v ss 96 avdd3 129 ad30 31 perr 64 eraclk 97 xtal1 130 v ssb 32 serr 65 era7 98 avss2 131 ad29 33 v ddb 66 era6 99 xtal2 132 ad28 p r e l i m i n a r y amd 15 AM79C970A pin designations - 132 pin pqfp listed by group pin name pin function type driver no. of pins pci bus interface ad[31:0] address/data bus io ts3 32 c/ be [3:0] bus command/byte enable io ts3 4 clk bus clock i n/a 1 devsel device select io sts6 1 frame cycle frame io sts6 1 gnt bus grant i n/a 1 idsel initialization device select i n/a 1 inta interrupt io ts6 1 irdy initiator ready io sts6 1 lock bus lock i n/a 1 par parity io ts3 1 perr parity error io sts6 1 req bus request io ts3 1 rst reset i n/a 1 serr system error io ts6 1 stop stop io sts6 1 trdy target ready io sts6 1 board interface led1 led1 o led 1 led2 led2 o led 1 led3 led3 o led 1 sleep sleep mode i n/a 1 xtal1 crystal input i n/a 1 xtal2 crystal output o xtal 1 microwire eeprom interface eecs microwire serial eeprom chip select o o6 1 eedi microwire serial eeprom data in o led 1 eedo microwire address eeprom data out i n/a 1 eesk microwire serial prom clock io led 1 expansion rom interface era[7:0] expansion rom address bus o o6 8 eraclk expansion rom address clock o o6 1 erd[7:0] expansion rom data bus i n/a 8 eroe expansion rom output enable o o6 1 amd p r e l i m i n a r y 16 AM79C970A pin designations - 132 pin pqfp listed by group pin name pin function type driver no. of pins pci bus interface attachment unit interface (aui) ci+/ci aui collision differential pair i n/a 2 di+/di aui data in differential pair i n/a 2 do+/do aui data out differential pair o do 2 dxcvr disable transceiver o o6 1 10base t interface lnkst link status o led 1 rxd+/rxd- receive differential pair i n/a 2 txd+/txd- transmit differential pair o tdo 2 txp+/txp- transmit pre-distortion differential pair o tpo 2 general purpose serial interface (gpsi) clsn collision i n/a 1 rxen receive enable i n/a 1 rxdat receive data i n/a 1 rxclk receive clock i n/a 1 txclk transmit clock i n/a 1 txdat transmit data o o6 1 txen transmit enable o o6 1 external address detection interface (eadi) ear external address reject low i n/a 1 sfbd start frame byte delimiter o led 1 srd serial receive data o led 1 srdclk serial receive data clock o led 1 ieee 1149.1 test access port interface (jtag) tck test clock i n/a 1 tdi test data in i n/a 1 tdo test data out o ts6 1 tms test mode select i n/a 1 test interface nout nand tree test output o o6 1 power supplies av dd analog power p n/a 4 av ss analog ground p n/a 2 v dd digital power p n/a 6 v ss digital ground p n/a 12 v ddb i/o buffer power p n/a 4 v ssb i/o buffer ground p n/a 8 p r e l i m i n a r y amd 17 AM79C970A pin designations - 144 pin tqfp listed by pin number pin no. name pin no. name pin no. name pin no. name 1 nc 37 nc 73 nc 109 nc 2 v ddb 38 par 74 v ss 110 avss1 3 ad27 39 c/ be1 75 era5 111 do- 4 ad26 40 ad15 76 era4 112 do+ 5 v ssb 41 v ssb 77 era3 113 avdd1 6 ad25 42 ad14 78 era2 114 di 7 ad24 43 ad13 79 v ss 115 di+ 8 c/ be3 44 ad12 80 era1 116 ci- 9 v dd 45 ad11 81 era0 117 ci+ 10 tdi 46 ad10 82 erd7/txdat 118 avdd2 11 idsel 47 v ssb 83 v dd 119 v dd 12 v ssb 48 ad9 84 erd6/txen 120 eedo/ led3 /srd 13 ad23 49 ad8 85 erd5 121 eedi/ lnkst 14 ad22 50 v ddb 86 v ss 122 eesk/ led1 /sfbd 15 v ssb 51 c/ be0 87 erd4/txclk 123 v ss 16 ad21 52 ad7 88 erd3/clsn 124 eecs 17 ad20 53 ad6 89 v ss 125 sleep 18 v ddb 54 v ssb 90 erd2/rxen 126 reserved 19 ad19 55 ad5 91 v dd 127 inta 20 ad18 56 ad4 92 erd1/rxclk 128 tck 21 v ssb 57 ad3 93 erd0/rxdat 129 v ss 22 ad17 58 ad2 94 led2 /srdclk 130 rst 23 ad16 59 v ssb 95 v ss 131 clk 24 c/ be2 60 ad1 96 rxd- 132 v dd 25 frame 61 ad0 97 rxd+ 133 gnt 26 irdy 62 ear 98 avdd4 134 tms 27 trdy 63 v dd 99 txp 135 v ss 28 devsel 64 eroe 100 txd- 136 req 29 stop 65 v ss 101 txp+ 137 tdo 30 lock 66 dxcvr/nout 102 txd+ 138 ad31 31 v ss 67 v ss 103 avdd3 139 ad30 32 perr 68 eraclk 104 xtal1 140 v ssb 33 serr 69 era7 105 avss2 141 ad29 34 v ddb 70 era6 106 xtal2 142 ad28 35 nc 71 nc 107 nc 143 nc 36 nc 72 nc 108 nc 144 nc nc indicates no connect amd p r e l i m i n a r y 18 AM79C970A pin designations - 144 pin tqfp listed by group pin name pin function type driver no. of pins pci bus interface ad[31:0] address/data bus io ts3 32 c/ be [3:0] bus command/byte enable io ts3 4 clk bus clock i n/a 1 devsel device select io sts6 1 frame cycle frame io sts6 1 gnt bus grant i n/a 1 idsel initialization device select i n/a 1 inta interrupt io ts6 1 irdy initiator ready io sts6 1 lock bus lock i n/a 1 par parity io ts3 1 perr parity error io sts6 1 req bus request io ts3 1 rst reset i n/a 1 serr system error io ts6 1 stop stop io sts6 1 trdy target ready io sts6 1 board interface led1 led1 o led 1 led2 led2 o led 1 led3 led3 o led 1 sleep sleep mode i n/a 1 xtal1 crystal input i n/a 1 xtal2 crystal output o xtal 1 microwire eeprom interface eecs microwire serial eeprom chip select o o6 1 eedi microwire serial eeprom data in o led 1 eedo microwire address eeprom data out i n/a 1 eesk microwire serial prom clock io led 1 expansion rom interface era[7:0] expansion rom address bus o o6 8 eraclk expansion rom address clock o o6 1 erd[7:0] expansion rom data bus i n/a 8 eroe expansion rom output enable o o6 1 p r e l i m i n a r y amd 19 AM79C970A pin designations - 144 pin tqfp listed by group pin name pin function type driver no. of pins pci bus interface attachment unit interface (aui) ci+/ci aui collision differential pair i n/a 2 di+/di aui data in differential pair i n/a 2 do+/do aui data out differential pair o do 2 dxcvr disable transceiver o o6 1 10base t interface lnkst link status o led 1 rxd+/rxd- receive differential pair i n/a 2 txd+/txd- transmit differential pair o tdo 2 txp+/txp- transmit pre-distortion differential pair o tpo 2 general purpose serial interface (gpsi) clsn collision i n/a 1 rxen receive enable i n/a 1 rxdat receive data i n/a 1 rxclk receive clock i n/a 1 txclk transmit clock i n/a 1 txdat transmit data o o6 1 txen transmit enable o o6 1 external address detection interface (eadi) ear external address reject low i n/a 1 sfbd start frame byte delimiter o led 1 srd serial receive data o led 1 srdclk serial receive data clock o led 1 ieee 1149.1 test access port interface (jtag) tck test clock i n/a 1 tdi test data in i n/a 1 tdo test data out o ts6 1 tms test mode select i n/a 1 test interface nout nand tree test output o o6 1 power supplies av dd analog power p n/a 4 av ss analog ground p n/a 2 v dd digital power p n/a 6 v ss digital ground p n/a 12 v ddb i/o buffer power p n/a 4 v ssb i/o buffer ground p n/a 8 amd p r e l i m i n a r y 20 AM79C970A pin designations listed by driver type the next table describes the various types of drivers that are used in the pcnet?pci ii controller: name type i ol (ma) i oh (ma) load (pf) led led 12 0.4 50 o6 totem pole 6 0.4 50 od6 open drain 6 n/a 50 sts6 sustained tri state tm 6 250 ts3 tri state 3 2 50 ts6 tri state 6 2 50 all i ol and i oh values shown in the table above apply to 5 v signaling. see the section dc characteristics" for the values applying to 3.3 v signaling. a sustained tri state signal is a low active signal that is driven high for one clock period before it is left floating. do, tdo and tpo are differential output drivers. the characteristic of these and the xtal output are de scribed in the section dc characteristics". p r e l i m i n a r y amd 21 AM79C970A ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of: temperature range c = commercial (0 c to +70 c) package type k = plastic quad flat pack (pqb132) v = thin quad flat pack (pdl144) speed option not applicable device number/description AM79C970A pcnet pci ii single chip full duplex controller for pci local bus AM79C970A valid combinations kc, kc\w, vc, vc\w valid combinations optional processing blank = standard processing AM79C970A k c valid combinations list configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. \w alternate packaging option \w = trimmed and formed in a tray amd p r e l i m i n a r y 22 AM79C970A pin description pci interface ad[31:0] address and data input/output address and data are multiplexed on the same bus in terface pins. during the first clock of a transaction ad[31:0] contain a physical address (32 bits). during the subsequent clocks ad[31:0] contain data. byte or dering is little endian by default. ad[7:0] are defined as least significant byte and ad[31:24] are defined as the most significant byte. for fifo data transfers, the pcnet pci ii controller can be programmed for big endian byte ordering. see csr3, bit 2 (bswp) for more details. during the address phase of the transaction, when the pcnet pci ii controller is a bus master, ad[31:2] will address the active double word (dword). the pcnet pci ii controller always drives ad[1:0] to `00' dur ing the address phase indicating linear burst order. when the pcnet pci ii controller is not a bus master, the ad[31:0] lines are continuously monitored to deter mine if an address match exists for slave transfers. during the data phase of the transaction, ad[31:0] are driven by the pcnet pci ii controller when performing bus master write and slave read operations. data on ad[31:0] is latched by the pcnet pci ii controller when performing bus master read and slave write operations. when rst is active, ad[31:0] are inputs for nand tree testing. c/ be [3:0] bus command and byte enables input/output bus command and byte enables are multiplexed on the same bus interface pins. during the address phase of the transaction, c/ be [3:0] define the bus command. during the data phase c/ be [3:0] are used as byte en- ables. the byte enables define which physical byte lanes carry meaningful data. c/ be 0 applies to byte 0 (ad[7:0]) and c/ be 3 applies to byte 3 (ad[31:24]). the function of the byte enables is independent of the byte ordering mode (bswp, csr3, bit 2). when rst is active, c/ be [3:0] are inputs for nand tree testing. clk clock input this clock is used to drive the system bus interface and the internal buffer management unit. all bus signals are sampled on the rising edge of clk and all parameters are defined with respect to this edge. the pcnet-pci ii controller operates over a range of 0 mhz to 33 mhz. this clock is not used to drive the network functions. when rst is active, clk is an input for nand tree testing. devsel device select input/output the pcnet-pci ii controller drives devsel when it detects a transaction that selects the device as a target. the device samples devsel to detect if a target claims a transaction that the pcnet-pci ii controller has initiated. when rst is active, devsel is an input for nand tree testing. frame cycle frame input/output frame is driven by the pcnet-pci ii controller when it is the bus master to indicate the beginning and duration of a transaction. frame is asserted to indicate a bus transaction is beginning. frame is asserted while data transfers continue. frame is deasserted before the fi- nal data phase of a transaction. when the pcnet-pci ii controller is in slave mode, it samples frame to deter- mine the address phase of transaction. when rst is active, frame is an input for nand tree testing. gnt bus grant input this signal indicates that the access to the bus has been granted to the pcnet-pci ii controller. the pcnet-pci ii controller supports bus parking. when the pci bus is idle and the system arbiter asserts gnt without an active req from the pcnet-pci ii controller, the device will drive the ad[31:0], c/ be [3:0] and par lines. when rst is active, gnt is an input for nand tree testing. idsel initialization device select input this signal is used as a chip select for the pcnet-pci ii controller during configuration read and write transactions. when rst is active, idsel is an input for nand tree testing. p r e l i m i n a r y amd 23 AM79C970A inta interrupt request input/output an attention signal which indicates that one or more of the following status flags is set: babl, exdint, idon, jab, merr, miss, mfco, mpint, rcvcco, rint, sint, slpint, tint, txstrt and uint. each status flag has either a mask or an enable bit which allows for suppression of inta assertion. the flags have the following meaning: table 1. interrupt flags babl babble exdint excessive deferral idon initialization done jab jabber merr memory error miss missed frame mfco missed frame count overflow mpint magic packet interrupt rcvcco receive collision count overflow rint receive interrupt slpint sleep interrupt sint system error tint transmit interrupt txstrt transmit start uint user interrupt by default inta is an open-drain output. for applica- tions that need a high-active edge sensitive interrupt signal, the inta pin can be configured for this mode by setting intlevel (bcr2, bit 7) to one. when rst is active, inta is an input for nand tree testing. irdy initiator ready input/output irdy indicates the ability of the initiator of the transac- tion to complete the current data phase. irdy is used in conjunction with trdy . wait states are inserted until both irdy and trdy are asserted simultaneously. a data phase is completed on any clock when both irdy and trdy are asserted. when the pcnet-pci ii controller is a bus master, it as- serts irdy during all write data phases to indicated that valid data is present on ad[31:0]. during all read data phases the device asserts irdy to indicate that it is ready to accept the data. when the pcnet-pci ii controller is the target of a trans- action, it checks irdy during all write data phases to de- termine if valid data is present on ad[31:0]. during all read data phases the device checks irdy to determine if the initiator is ready to accept the data. when rst is active, irdy is an input for nand tree testing. lock lock input in slave mode, lock is an input to the pcnet-pci ii con- troller. a bus master can lock the device to guarantee an atomic operation that requires multiple transactions. the pcnet-pci ii controller will never assert lock as a master. when rst is active, lock is an input for nand tree testing. par parity input/output parity is even parity across ad[31:0] and c/ be [3:0]. when the pcnet-pci ii controller is a bus master, it gen- erates parity during the address and write data phases. it checks parity during read data phases. when the pcnet-pci ii controller operates in slave mode, it checks parity during every address phase. when it is the target of a cycle, it checks parity during write data phases and it generates parity during read data phases. when rst is active, par is an input for nand tree testing. perr parity error input/output during any slave write transaction and any master read transaction, the pcnet-pci ii controller asserts perr when it detects a data parity error and reporting of the error is enabled by setting perren (pci command register, bit 6) to one. during any master write transac- tion the pcnet-pci ii controller monitors perr to see if the target reports a data parity error. when rst is active, perr is an input for nand tree testing. req bus request input/output the pcnet-pci ii controller asserts req pin as a signal that it wishes to become a bus master. req is driven high when the pcnet-pci ii controller does not request the bus. when rst is active, req is an input for nand tree testing. rst reset input when rst is asserted low, then the pcnet-pci ii con- troller performs an internal system reset of the type amd p r e l i m i n a r y 24 AM79C970A h_reset (hardware_reset). rst must be held for a minimum of 30 clock periods. while in the h_re- set state, the pcnet-pci ii controller will disable or deassert all outputs. rst may be asynchronous to clk when asserted or deasserted. it is recommended that the deassertion be synchronous to guarantee clean and bounce free edge. when rst is active, nand tree testing is enabled. all pci interface pins are in input mode. the result of the nand tree testing can be observed on the nout output (pin 62). serr system error input/output during any slave transaction, the pcnet-pci ii controller asserts serr when it detects an address parity error and reporting of the error is enabled by setting perren (pci command register, bit 6) and serren (pci com- mand register, bit 8) to one. by default serr is an open-drain output. for compo- nent test it can be programmed to be an active-high to- tem-pole output. when rst is active, serr is an input for nand tree testing. stop stop input/output in slave mode, the pcnet-pci ii controller drives the stop signal to inform the bus master to stop the current transaction. in bus master mode, the pcnet-pci ii con- troller checks stop to determine if the target wants to disconnect the current transaction. when rst is active, stop is an input for nand tree testing. trdy target ready input/output trdy indicates the ability of the target of the transaction to complete the current data phase. trdy is used in conjunction with irdy . wait states are inserted until both irdy and trdy are asserted simultaneously. a data phase is completed on any clock when both irdy and trdy are asserted. when the pcnet-pci ii controller is a bus master, it checks trdy during all read data phases to determine if valid data is present on ad[31:0]. during all write data phases the device checks trdy to determine if the tar- get is ready to accept the data. when the pcnet-pci ii controller is the target of a trans- action, it asserts trdy during all read data phases to in- dicate that valid data is present on ad[31:0]. during all write data phases the device asserts trdy to indicate that it is ready to accept the data. when rst is active, trdy is an input for nand tree testing. board interface led1 led1 output this output is designed to directly drive an led. by de- fault, led1 indicates receive activity on the network. this pin can also be programmed to indicate other network status (see bcr5). the led1 pin polarity is programmable, but by default, it is active low. note that the led1 pin is multiplexed with the eesk and sfbd pins. led2 led2 output this output is designed to directly drive an led. by de- fault, led2 indicates correct receive polarity on the 10base-t interface. this pin can also be programmed to indicate other network status (see bcr6). the led2 pin polarity is programmable, but by default, it is active low. note that the led2 pin is multiplexed with the srdclk pin. led3 led3 output this output is designed to directly drive an led. by de- fault, led3 indicates transmit activity on the network. this pin can also be programmed to indicate other net- work status (see bcr7). the led3 pin polarity is pro- grammable, but by default, it is active low. note that the led3 pin is multiplexed with the eedo and srd pins. special attention must be given to the external circuitry attached to this pin. when this pin is used to drive an led while an eeprom is used in the system, then buff- ering is required between the led3 pin and the led cir- cuit. if an led circuit were directly attached to this pin, it would create an i ol requirement that could not be met by the serial eeprom attached to this pin. if no eeprom is included in the system design, then the led3 signal may be directly connected to an led with- out buffering. for more details regarding led connec- tion, see the section led support. sleep sleep input when sleep is asserted, the pcnet-pci ii controller performs an internal system reset of the s_reset type and then proceeds into a power savings mode. all pcnet-pci ii controller outputs will be placed in their normal reset condition. all pcnet-pci ii controller inputs p r e l i m i n a r y amd 25 AM79C970A will be ignored except for the sleep pin itself. deasser- tion of sleep results in wake-up. the system must re- frain from starting the network operations of the pcnet-pci ii controller device for 0.5 s following the deassertion of the sleep signal in order to allow inter- nal analog circuits to stabilize. both clk and xtal1 inputs must have valid clock sig- nals present in order for the sleep command to take effect. the sleep pin should not be asserted during power supply ramp-up. if it is desired that sleep be asserted at power up time, then the system must delay the asser- tion of sleep until three clock cycles after the comple- tion of a hardware reset operation. the sleep pin must not be left unconnected. it should be tied to vdd, if the power savings mode is not used. xtal1 crystal oscillator in input the internal clock generator uses a 20 mhz crystal that is attached to the pins xtal1 and xtal2. the network data rate is one-half of the crystal frequency. xtal1 may alternatively be driven using an external 20 mhz cmos level clock signal. refer to the section external crystal characteristics for more details. note that when the pcnet-pci ii controller is in coma mode, there is an internal 22 k w resistor from xtal1 to ground. if an external source drives xtal1, some power will be consumed driving this resistor. if xtal1 is driven low at this time power consumption will be mini mized. in this case, xtal1 must remain active for at least 30 cycles after the assertion of sleep and deassertion of req . xtal2 crystal oscillator out output the internal clock generator uses a 20 mhz crystal that is attached to the pins xtal1 and xtal2. the network data rate is one-half of the crystal frequency. if an exter- nal clock source is used on xtal1, then xtal 2 should be left unconnected. microwire eeprom interface eecs eeprom chip select output this pin is designed to directly interface to a serial eeprom that uses the microwire interface protocol. eecs is connected to the microwire eeprom chip se- lect pin. it is controlled by either the pcnet-pci ii con- troller during command portions of a read of the entire eeprom, or indirectly by the host system by writing to bcr19, bit 2. eedi eeprom data in output this pin is designed to directly interface to a serial eeprom that uses the microwire interface protocol. eedi is connected to the microwire eeprom data input pin. it is controlled by either the pcnet-pci ii controller during command portions of a read of the entire eeprom, or indirectly by the host system by writing to bcr19, bit 0. note that the eedi pin is multiplexed with the lnkst pin. eedo eeprom data out input this pin is designed to directly interface to a serial eeprom that uses the microwire interface protocol. eedo is connected to the microwire eeprom data out- put pin. it is controlled by either the pcnet-pci ii control- ler during command portions of a read of the entire eeprom, or indirectly by the host system by reading from bcr19, bit 0. note that the eedo pin is multiplexed with the led3 and srd pins. eesk eeprom serial clock input/output this pin is designed to directly interface to a serial eeprom that uses the microwire interface protocol. eesk is connected to the microwire eeprom clock pin. it is controlled by either the pcnet-pci ii controller di- rectly during a read of the entire eeprom, or indirectly by the host system by writing to bcr19, bit 1. note that the eesk pin is multiplexed with the led1 and sfbd pins. the eesk pin is also used during eeprom auto-detec- tion to determine whether or not an eeprom is present at the pcnet-pci ii controller microwire interface. at the rising edge of clk during the last clock during which rst is asserted, eesk is sampled to determine the value of the eedet bit in bcr19. a sampled high value means that an eeprom is present, and eedet will be set to one. a sampled low value means that an eeprom is not present, and eedet will be cleared to zero. see the section eeprom auto-detection for more details. if no led circuit is to be attached to this pin, then a pull up or pull down resistor must be attached instead, in or- der to resolve the eedet setting. amd p r e l i m i n a r y 26 AM79C970A expansion rom interface era[7:0] expansion rom address output these pins provide the address to the expansion rom. when eroe is asserted and eraclk is driven high, era[7:0] contain the upper 8 bits of the expansion rom address. they must be latched externally. when eroe is asserted and eraclk is low, era[7:0] contain the lower 8 bits of the expansion rom address. all era outputs are forced to a constant level to con- serve power while no access to the expansion rom is performed. eraclk expansion rom address clock output when eroe is asserted and eraclk is driven high, era[7:0] contain the upper 8 bits of the expansion rom address. eraclk is used to latch the address bits externally. both '373 (transparent latch) and '374 (d flip-flop) types of address latch are supported. erd[7:0] expansion rom data input data from the expansion rom is transferred on erd[7:0]. when eroe is high, the erd[7:0] inputs are internally disabled and can be left floating. note that the erd[7:0] pins are multiplexed with the gpsi interface. eroe expansion rom output enable output this signal is asserted when the expansion rom is read. attachment unit interface ci collision in input ci is a differential input pair signaling the pcnet pci ii controller that a collision has been detected on the net work media, indicated by the ci inputs being driven with a 10 mhz pattern of sufficient amplitude and pulse width to meet iso 8802 3 (ieee/ansi 802.3) stan dards. operates at pseudo ecl levels. di data in input di is a differential input pair to the pcnet pci ii control ler carrying manchester encoded data from the network. operates at pseudo ecl levels. do data out output do is a differential output pair from the pcnet pci ii controller for transmitting manchester encoded data to the network. operates at pseudo ecl levels. dxcvr disable transceiver output the dxcvr signal is provided to power down an exter nal transceiver or dc to dc converter in designs that provide more than one network connection. the polarity of the asserted state of the dxcvr output is controlled by dxcvrpol (bcr2, bit 4). by default, the dxcvr output is high when asserted. when the 10base t interface is the active network port, the dxcvr output is always deasserted. when the aui or gpsi interface is the active network port, the assertion of the dxcvr output is controlled by the setting of dxcvrctl (bcr2, bit 5). note that the dxcvr pin is multiplexed with the nout pin. twisted pair interface lnkst link status output this output is designed to directly drive an led. by de- fault, lnkst indicates an active link connection on the 10base-t interface. this pin can also be programmed to indicate other network status (see bcr4). the lnkst pin polarity is programmable, but by default, it is active low. note that the lnkst pin is multiplexed with the eedi pin. rxd 10base t receive data input 10base t port differential receivers. txd 10base t transmit data output 10base t port differential drivers. txp 10base t pre distortion control output these outputs provide transmit pre distortion control in conjunction with the 10base t port differential drivers. general purpose serial interface clsn collision input clsn is an input, indicating that a collision has occurred on the network. note that the clsn pin is multiplexed with the erd3 pin. rxclk receive clock input rxclk is an input. rising edges of the rxclk signal are used to sample the data on the rxdat input when ever the rxen input is high. p r e l i m i n a r y amd 27 AM79C970A note that the rxclk pin is multiplexed with the erd1 pin. rxdat receive data input rxdat is an input. rising edges of the rxclk signal are used to sample the data on the rxdat input when ever the rxen input is high. note that the rxdat pin is multiplexed with the erd0 pin. rxen receive enable input rxen is an input. when this signal is high, it indicates to the core logic that the data on the rxdat input pin is valid. note that the rxen pin is multiplexed with the erd2 pin. txclk transmit clock input txclk is an input, providing a clock signal for mac ac tivity, both transmit and receive. rising edges of the txclk can be used to validate txdat output data. note that the txclk pin is multiplexed with the erd4 pin. txdat transmit data output txdat is an output, providing the serial bit stream for transmission, including preamble, sfd data and fcs field, if applicable. txdat floats when the gpsi inter face is not enabled. note that the txdat pin is multiplexed with the erd7 pin. txen transmit enable output txen is an output, providing an enable signal for trans mission. data on the txdat pin is not valid unless the txen signal is high. txen should have an external pull down resistor attached (e.g. 3.3 k w ) to ensure the output is held inactive until the gpsi interface is enabled. note that the txen pin is multiplexed with the erd6 pin. external address detection interface ear external address reject low input the incoming frame will be checked against the inter- nally active address detection mechanisms and the result of this check will be ord with the value on the ear pin. the ear pin is defined as reject . the pin value is ored with the internal address detection re- sult to determine if the current frame should be accepted or rejected. the ear pin is internally pulled-up and can be left un- connected, if the eadi interface is not used. sfbd start framebyte delimiter output an initial rising edge on the sfbd signal indicates that a start of frame delimiter has been detected. the serial bit stream will follow on the srd signal, commencing with the destination address field. sfbd will go high for 4 bit times (400 ns) after detecting the second one in the sfd (start of frame delimiter) of a received frame. sfbd will subsequently toggle every 400 ns (1.25 mhz frequency) with each rising edge indicating the first bit of each subsequent byte of the received serial bit stream. sfbd will be inactive during frame transmission. note that the sfbd pin is multiplexed with the eesk and led1 pins. srd serial receive data output srd is the decoded nrz data from the network. this signal can be used for external address detection. when the 10base-t port is selected, transitions on srd will only occur during receive activity. when the aui or gpsi port is selected, transitions on srd will occur during both transmit and receive activity. note that the srd pin is multiplexed with the eedo and led3 pins. srdclk serial receive data clock output serial receive data is synchronous with reference to srdclk. when the 10base-t port is selected, transi- tions on srdclk will only occur during receive activity. when the aui or gpsi port is selected, transitions on srdclk will occur during both transmit and receive activity. note that the srdclk pin is multiplexed with the led2 pin. ieee 1149.1 test access port interface tck test clock input tck is the clock input for the boundary scan test mode operation. it can operate at a frequency of up to 10 mhz. tck has an internal pull-up resistor. the tck input amd p r e l i m i n a r y 28 AM79C970A operates in the same signaling environment as the pci bus interface. tdi test data in input tdi is the test data input path to the pcnet pci ii con troller. the pin has an internal pull up resistor. the tdi input operates in the same signaling environment as the pci bus interface. tdo test data out output tdo is the test data output path from the pcnet pci ii controller. the pin is tri stated when the jtag port is in active. the tdo output operates in the same signaling environment as the pci bus interface. tms test mode select input a serial input bit stream on the tms pin is used to define the specific boundary scan test to be executed. the pin has an internal pull up resistor. the tms input operates in the same signaling environment as the pci bus interface. test interface nout nand tree out output when rst is asserted, the results of the nand tree testing can be observed on the nout pin. note that the nout pin is multiplexed with the dxcvr pin. power supply pins av dd analog power (4 pins) power there are four analog +5 v supply pins. special atten- tion should be paid to the printed circuit board layout to avoid excessive noise on these lines. refer to appendix b and the pcnet family board design and layout recommendations application note (pid #19595a) for details. av ss analog ground (2 pins) power there are two analog ground pins. special attention should be paid to the printed circuit board layout to avoid excessive noise on these lines. refer to appendix b and the pcnet family board design and layout recommendations application note (pid #19595a) for details. v dd digital power (6 pins) power there are six power supply pins that are used by the in- ternal digital circuitry. all v dd pins must be connected to a +5 v supply. v ddb i/o buffer power (4 pins) power there are four power supply pins that are used by the pci bus input/output buffer drivers. in a system with 5 v signaling environment, all v ddb pins must be connected to a +5 v supply. in a system with 3.3 v signaling nvironment, all v ddb pins must be connected to a +3.3 v supply. v ss digital ground (12 pins) ground there are 12 ground pins that are used by the internal digital circuitry. v ssb i/o buffer ground (8 pins) ground there are 8 ground pins that are used by the pci bus in- put/output buffer drivers. p r e l i m i n a r y amd 29 AM79C970A basic functions system bus interface function the pcnet pci ii controller is designed to operate as a bus master during normal operations. some slave i/o accesses to the pcnet pci ii controller are required in normal operations as well. initialization of the pcnet pci ii controller is achieved through a combina tion of pci configuration space accesses, bus slave ac cesses, bus master accesses and an optional read of a serial eeprom that is performed by the pcnet pci ii controller. the eeprom read operation is performed through the microwire interface. the iso 8802 3 (ieee/ansi 802.3) ethernet address may reside within the serial eeprom. some pcnet pci ii controller con figuration registers may also be programmed by the eeprom read operation. the address prom, on chip bus configuration regis ters, and the ethernet controller registers occupy 32 bytes of address space. both, i/o and memory mapped i/o access are supported. base address registers in the pci configuration space allow locating the address space on a wide variety of starting addresses. for diskless stations, the pcnet pci ii controller sup ports an expansion rom of up to 64 kbytes in size. the host can map the expansion rom to any memory ad dress that aligns to a 64k boundary by modifying the expansion rom base address register in the pci con figuration space. software interface the software interface to the pcnet pci ii controller is divided into three parts. one part is the pci configura tion registers. they are used to identify the pcnet pci ii controller, and are also used to setup the configuration of the device. the setup information includes the i/o or memory mapped i/o base address, mapping of the expansion rom and the routing of the pcnet pci ii controller interrupt channel. this allows for a jumperless implementation. the second portion of the software interface is the direct access to the i/o resources of the pcnet pci ii control ler. the pcnet pci ii controller occupies 32 bytes of ad dress space that must begin on a 32 byte block boundary. the address space can be mapped into both i/o or memory space (memory mapped i/o). the i/o base address register in the pci configuration space defines the start address of the address space if it is mapped to i/o space. the memory mapped i/o base address register defines the start address of the ad dress space if it is mapped to memory space. the 32 byte address space is used by the software to pro gram the pcnet pci ii controller operating mode, en able and disable various features, monitor operating status, and request particular functions to be executed by the pcnet pci ii controller. the third portion of the software interface is the descrip tor and buffer areas that are shared between the soft ware and the pcnet pci ii controller during normal network operations. the descriptor area boundaries are set by the software and do not change during normal network operations. there is one descriptor area for re ceive activity and there is a separate area for transmit activity. the descriptor space contains relocatable pointers to the network frame data and it is used to trans fer frame status from the pcnet pci ii controller to the software. the buffer areas are locations that hold frame data for transmission or that accept frame data that has been received. network interfaces the pcnet pci ii controller can be connected to an 802.3 network via one of three network interfaces. the attachment unit interface (aui) provides an iso 8802 3 (ieee/ansi 802.3) compliant differential interface to a remote mau or an on board transceiver. the 10base t interface provides a twisted pair ethernet port. while in auto selection mode, the interface in use is determined by an auto sensing mechanism which checks the link status on the 10base t port. if there is no active link status, then the device assumes an aui connection. the general purpose serial interface (gpsi) allows bypassing the manchester encoder/de coder (mendec). the pcnet pci ii controller implements half or full du plex ethernet over all three network interfaces. amd p r e l i m i n a r y 30 AM79C970A detailed functions slave bus interface unit the slave bus interface unit (biu) controls all accesses to the pci configuration space, the control and status registers (csr), the bus configuration registers (bcr), the address prom (aprom) locations and the expansion rom. the table below shows the response of the pcnet pci ii controller to each of the pci com mands in slave mode. table 2. slave commands c[3:0] command use 0000 interrupt acknowledge not used 0001 special cycle not used 0010 i/o read read of csr, bcr and aprom 0011 i/o write write to csr, bcr and aprom 0100 reserved 0101 reserved 0110 memory read memory mapped i/o read of csr, bcr and aprom read of the expansion rom 0111 memory write memory mapped i/o write of csr, bcr and aprom dummy write to the expansion rom 1000 reserved 1001 reserved 1010 configuration read read of the configuration space 1011 configuration write write to the configuration space 1100 memory read multiple aliased to memory read 1101 dual address cycle not used 1110 memory read line aliased to memory read 1111 memory write invalidate aliased to memory write slave configuration transfers the host can access the pcnet pci ii controller pci configuration space with a configuration read or write command. the pcnet pci ii controller will assert devsel during the address phase when idsel is as- serted, ad[1:0] are both zero, and the access is a con- figuration cycle. ad[7:2] select the dword location in the configuration space. the pcnet-pci ii controller ig- nores ad[10:8], because it is a single function device. ad[31:11] are don't care. the active bytes within a dword are determined by the byte enable signals. 8-bit, 16-bit and 32-bit transfers are supported. devsel is asserted two clock cycles after the host has asserted frame . all configuration cycles are of fixed length. the pcnet-pci ii controller will as- sert trdy on the 4th clock of the data phase. the pcnet-pci ii controller does not support burst transfers for access to configuration space. when the host keeps frame asserted for a second data phase, the pcnet-pci ii controller will disconnect the transfer. when the host tries to access the pci configuration space while the automatic read of the eeprom after h_reset is on-going, the pcnet-pci ii controller will terminate the access on the pci bus with a disconnect/ retry response. the pcnet-pci ii controller supports fast back-to-back transactions to different targets. this is indicated by the fast back-to-back capable bit (pci status register, bit 7), which is hardwired to one. the pcnet-pci ii con- troller is capable of detecting a configuration cycle even when its address phase immediately follows the data phase of a transaction to a different target without any idle state in-between. there will be no contention on the devsel , trdy and stop signals, since the pcnet-pci ii controller asserts devsel on the second clock after frame is asserted (medium timing). ad31 ad11 ad10 ad8 ad7 ad2 ad1 ad0 don't care don't care dword index 0 0 p r e l i m i n a r y amd 31 AM79C970A 19436a 4 frame clk ad irdy trdy c/ be devsel stop idsel 1 23456 1010 par par par be data addr 7 figure 1. slave configuration read amd p r e l i m i n a r y 32 AM79C970A 19436a 5 frame clk ad irdy trdy c/ be devsel stop idsel 1 23456 1011 par par par be data addr 7 figure 2. slave configuration write slave i/o transfers after the pcnet pci ii controller is configured as an i/o device by setting ioen (for regular i/o mode) or memen (for memory mapped i/o mode) in the pci command register, it starts monitoring the pci bus for access to its csr, bcr or eeprom locations. if config ured for regular i/o mode, the pcnet pci ii controller will look for an address that falls within its 32 bytes of i/o address space (starting from the i/o base address). the pcnet pci ii controller asserts devsel if it detects an address match and the access is an i/o cycle. if config- ured for memory mapped i/o mode, the pcnet-pci ii controller will look for an address that falls within its 32 bytes of memory address space (starting from the mem- ory mapped i/o base address). the pcnet-pci ii con- troller asserts devsel if it detects an address match and the access is a memory cycle. devsel is asserted two clock cycles after the host has asserted frame . the pcnet-pci ii controller will not assert devsel if it detects an address match, but the pci command is not of the correct type. in memory mapped i/o mode, the pcnet-pci ii controller aliases all accesses to the i/o re- sources of the command types memory read multiple and memory read line to the basic memory read command. all accesses of the type memory write and invalidate are aliased to the basic memory write com- mand. 8-bit, 16-bit and 32-bit non-burst transactions are supported. the pcnet-pci ii controller decodes only the upper 30 address lines to determine which i/o resource is accessed. the typical number of wait states added to a slave i/o or memory mapped i/o read or write access on the part of the pcnet-pci ii controller is 6 to 7 clock cycles, depending upon the relative phases of the internal buffer management unit clock and the clk signal, since the internal buffer management unit clock is a divide-by-two version of the clk signal. the pcnet-pci ii controller does not support burst transfers for access to its i/o resources. when the host keeps frame asserted for a second data phase, the pcnet-pci ii controller will disconnect the transfer. the pcnet-pci ii controller supports fast back-to-back transactions to different targets. this is indicated by the fast back-to-back capable bit (pci status register, p r e l i m i n a r y amd 33 AM79C970A bit 7), which is hardwired to one. the pcnet pci ii controller is capable of detecting an i/o or a memory mapped i/o cycle even when its address phase immedi ately follows the data phase of a transaction to a differ ent target, without any idle state in between. there will be no contention on the devsel , trdy and stop signals, since the pcnet-pci ii controller asserts devsel on the second clock after frame is asserted (medium timing). 19436a-6 frame clk ad irdy trdy c/ be devsel stop par addr 0010 par 1 2345678 10 9 11 data par be figure 3. slave read using i/o command amd p r e l i m i n a r y 34 AM79C970A 19436a 7 frame clk ad irdy trdy c/ be devsel stop par addr 0111 par 1 2345678 10 9 11 data par be figure 4. slave write using memory command expansion rom transfers the host must initialize the expansion rom base ad dress register at offset 30h in the pci configuration space with a valid address before enabling the access to the device. the base address must be aligned to a 64k boundary as indicated by romsize (pci expansion rom base address register, bits 15-11). the pcnet pci ii controller will not react to any access to the expansion rom until both memen (pci command reg ister, bit 1) and romen (pci expansion rom base ad dress register, bit 0) are set to one. after the expansion rom is enabled, the pcnet pci ii controller will assert devsel on all memory read accesses with an address between rombase and rombase + 64k C 4. the pcnet-pci ii controller aliases all accesses to the ex- pansion rom of the command types memory read multiple and memory read line to the basic memory read command. eight-bit, 16-bit and 32-bit read trans- fers are supported. since setting memen also enables memory mapped access to the i/o resources, attention must be given the pci memory mapped i/o base address register, before enabling access to the expansion rom. the host must set the pci memory mapped i/o base address register to a value that prevents the pcnet-pci ii controller from claiming any memory cycles not intended for it. the pcnet-pci ii controller will always read four bytes for every host expansion rom read access. trdy will not be asserted until all four bytes are loaded into an in- ternal scratch register. the cycle trdy is asserted de- pends on the programming of the expansion rom interface timing. the following figure assumes that romtmg (bcr18, bits 15C12) is at its default value. since the target latency for the expansion rom access is considerably long, the pcnet-pci ii controller discon- nects at the second data phase, when the host tries do to perform a burst read operation of the expansion rom. this behavior complies with the requirements for latency issues in the pci environment and allows other devices to get fair access to the bus. when the host tries to write to the expansion rom, the pcnet-pci ii controller will claim the cycle by asserting devsel . trdy will be asserted one clock cycle later. the write operation will have no effect. the pcnet-pci ii controller supports fast back-to-back transactions to different targets. this is indicated by the fast back-to-back capable bit (pci status register, p r e l i m i n a r y amd 35 AM79C970A bit 7), which is hardwired to one. the pcnet pci ii con troller is capable of detecting a memory cycle even when its address phase immediately follows the data phase of a transaction to a different target without any idle state in between. there will be no contention on the devsel , trdy and stop signals, since the pcnet-pci ii controller asserts devsel on the second clock after frame is asserted (medium timing). 19436a-8 frame clk ad irdy trdy c/ be devsel stop par devsel is sampled addr cmd par 1 2345 424344 45 data par be figure 5. expansion rom read exclusive access the host can lock a set of transactions to the pcnet pci ii controller. the lock allows exclusive ac cess to the device and can be used to guarantee atomic operations. the pcnet pci ii controller transitions from the unlocked to the locked state when lock is deas- serted during the address phase of a transaction that se- lects the device as the target. the controller stays in the locked state until both frame and lock are deasserted, or until the device signals a target abort. note that this protocol means the device locks itself on any normal transaction. the controller will unlock automatically at the end of a normal transaction, be- cause frame and lock will be deasserted. the lock spans over the whole slave address space. the lock only applies to slave accesses. the pcnet-pci ii controller might perform bus master cycles while being locked in slave mode. when another master tries to access the pcnet-pci ii controller while it is in the locked state, the device terminates the access with a disconnect/retry sequence. slave cycle termination there are three scenarios besides normal completion of a transaction where the pcnet-pci ii controller is the target of a slave cycle and it will terminate the access. disconnect when busy the pcnet-pci ii controller cannot service any slave ac- cess while it is reading the contents of the microwire eeprom. simultaneous access is not possible to avoid conflicts, since the microwire eeprom is used to initial- ize some of the pci configuration space locations and most of the bcrs. the microwire eeprom read opera- tion will always happen automatically after the deasser- tion of the rst pin. in addition, the host can start the amd p r e l i m i n a r y 36 AM79C970A read operation by setting the pread bit (bcr19, bit 14). while the eeprom read is on going, the pcnet pci ii controller will disconnect any slave access where it is the target by asserting stop together with devsel, while driving trdy high. stop will stay as- serted until the host removes frame . note that i/o and memory slave accesses will only be disconnected if they are enabled by setting the ioen or memen bit in the pci command register. without the enable bit set, the cycles will not be claimed at all. since h_reset clears the ioen and memen bits, for the automatic eeprom read after h_reset the discon- nect only applies to configuration cycles. a second situation where the pcnet-pci ii controller will generate a pci disconnect/retry cycle is when the host tries to access any of the i/o resources right after having read the reset register. since the access generates an internal reset pulse of about 1 m s in length, all further slave accesses will be deferred until the internal reset operation is completed. 19436a 9 frame clk ad irdy trdy c/ be devsel stop 1 2345 cmd par par par be data addr figure 6. disconnect of slave cycle when busy p r e l i m i n a r y amd 37 AM79C970A disconnect of burst transfer the pcnet pci ii controller does not support burst ac cess to the configuration space, the i/o resources, or to the expansion rom. the host indicates a burst transac tion by keeping frame asserted during the data phase. when the pcnet-pci ii controller sees frame and irdy asserted in the clock cycle before it wants to as- serts trdy , it also asserts stop at the same time. the transfer of the first data phase is still successful, since irdy and trdy are both asserted. 19436a-10 frame clk ad irdy trdy c/ be devsel stop 1 2345 be par par par be data 1st data figure 7. disconnect of slave burst transfer no host wait states amd p r e l i m i n a r y 38 AM79C970A when the host is not yet ready when the pcnet pci ii controller asserts trdy , the device will wait for the host to assert irdy . when the host asserts irdy and frame is still asserted, the pcnet-pci ii controller will finish the first data phase by deasserting trdy one clock later. at the same time, it will assert stop to signal a disconnect to the host. stop will stay asserted until the host removes frame . 19436a-11 frame clk ad irdy trdy c/ be devsel stop 1 23456 par be par par be data 1st data figure 8. disconnect of slave burst transfer host inserts wait states p r e l i m i n a r y amd 39 AM79C970A disconnect when locked when the pcnet pci ii controller is locked by one master and another master tries to access the control ler, the device will disconnect the access. when the pcnet pci ii controller is in the locked state and it sees lock asserted together with frame , it knows that another master tried to access it. the pcnet-pci ii con- troller will respond to the access by asserting stop to- gether with devsel while driving trdy high, thereby disconnecting the cycle. stop will stay asserted until the other master removes frame . 19436a-12 frame clk ad irdy trdy c/ be devsel stop 1 23456 cmd par par par be data addr lock figure 9. disconnect of slave cycle when locked amd p r e l i m i n a r y 40 AM79C970A parity error response when the pcnet pci ii controller is not the current bus master, it samples the ad[31:0], c/ be [3:0] and the par lines during the address phase of any pci command for a parity error. when it detects an address parity error, the controller sets perr (pci status register, bit 15) to one. when reporting of that error is enabled by setting serren (pci command register, bit 8) and perren (pci command register, bit 6) to one, the pcnet-pci ii controller also drives the serr signal low for one clock cycle and sets serr (pci status register, bit 14) to one. the assertion of serr follows the address phase by two clock cycles. the pcnet-pci ii controller will not assert devsel for a pci transaction that has an ad- dress parity error, when perren and serren are set to one. 19436a-13 frame clk ad serr c/ be devsel 1 2345 par par addr 1st data be cmd par figure 10. address parity error response p r e l i m i n a r y amd 41 AM79C970A during the data phase of an i/o write, memory mapped i/o write or configuration write command that selects the pcnet pci ii controller as target, the device samples the ad[31:0] and c/ be [3:0] lines for parity on the clock edge data is transferred. par is sampled in the follow- ing clock cycle. if a parity error is detected and reporting of that error is enabled by setting perren (pci com- mand register, bit 6) to one, perr is asserted one clock later. the parity error will always set perr (pci status register, bit 15) to one even when perren is cleared to zero. the pcnet-pci ii controller will finish a transaction that has a data parity error in the normal way by asserting trdy . the corrupted data will be writ- ten to the addressed location. figure 11 shows a transaction that suffered a parity error at the time data was transferred (clock 7, irdy and trdy are both asserted). perr is driven high at the beginning of the data phase and then drops low due to the parity error on clock 9, two clock cycles after the data was transferred. after perr is driven low, the pcnet-pci ii controller drives perr high for one clock cycle, since perr is a sustained tri-state signal. 19436a-14 frame clk ad irdy trdy c/ be devsel par addr cmd par 1 2345678 10 9 data par be perr figure 11. slave cycle data parity error response amd p r e l i m i n a r y 42 AM79C970A master bus interface unit the master bus interface unit (biu) controls the acquisition of the pci bus and all accesses to the initialization block, descriptor rings and the receive and transmit buffer memory. the table below shows the us age of pci commands by the pcnet pci ii controller in master mode. table 3. master commands c[3:0] command use 0000 interrupt acknowledge not used 0001 special cycle not used 0010 i/o read not used 0011 i/o write not used 0100 reserved 0101 reserved 0110 memory read read of the initialization block and descriptor rings read of the transmit buffer in non burst mode 0111 memory write write to the descriptor rings and to the receive buffer 1000 reserved 1001 reserved 1010 configuration read not used 1011 configuration write not used 1100 memory read multiple read of the transmit buffer in burst mode 1101 dual address cycle not used 1110 memory read line read of the transmit buffer in burst mode 1111 memory write invalidate not used bus acquisition the pcnet pci ii controller microcode will determine when a dma transfer should be initiated. the first step in any pcnet pci ii controller bus master transfer is to acquire ownership of the bus. this task is handled by synchronous logic within the biu. bus ownership is re quested with the req signal and ownership is granted by the arbiter through the gnt signal. figure 12 shows the pcnet-pci ii controller bus acquisition. req is asserted and the arbiter returns gnt while another bus master is transferring data. the pcnet-pci ii controller waits until the bus is idle ( frame and irdy deasserted) before it starts driving ad[31:0] and c/ be [3:0] on clock 5. frame is asserted at clock 5 indicating a valid address and command on ad[31:0] and c/ be [3:0]. the pcnet-pci ii controller does not use address stepping which is reflected by adstep (bit 7) in the pci command register being hardwired to zero. in burst mode, the deassertion of req depends on the setting of extreq (bcr18, bit 8). if extreq is cleared to zero , req is deasserted at the same time as frame is asserted. (the pcnet-pci ii controller never performs more than one burst transaction within a single bus mastership period). if extreq is set to one, the pcnet-pci ii controller does not deassert req until it starts the last data phase of the transaction. once asserted, req remains active until gnt has be- come active, independent of subsequent setting of the stop (csr0, bit 2) or spnd (csr5, bit 0). the asser- tion of h_reset or s_reset, however, will cause req to go inactive immediately. p r e l i m i n a r y amd 43 AM79C970A 19436a 15 frame clk ad irdy c/ be req gnt 1 2345 cmd addr figure 12. bus acquisition bus master dma transfers there are four primary types of dma transfers. the pcnet pci ii controller uses non burst as well as burst cycles for read and write access to the main memory. basic non burst read transfer by default, the pcnet pci ii controller uses non burst cycles in all bus master read operations. all pcnet pci ii controller non burst read accesses are of the pci command type memory read (type 6). note that during a non burst read operation, all byte lanes will al ways be active. the pcnet pci ii controller will inter nally discard unneeded bytes. the pcnet pci ii controller typically performs more than one non burst read transactions within a single bus mastership period. frame is dropped between con- secutive non-burst read cycles. req however stays asserted until frame is asserted for the last transaction. the pcnet-pci ii controller supports zero wait state read cycles. it asserts irdy immediately after the address phase and at the same time starts sampling devsel . amd p r e l i m i n a r y 44 AM79C970A the following figure shows two non burst read transac tions. the first transaction has zero wait states. in the second transaction, the target extends the cycle by as serting trdy one clock later. 19436a-16 frame clk ad irdy trdy c/ be devsel req gnt par devsel is sampled addr 0110 par 1 2345678 10 9 11 data addr data par par par 0000 0110 0000 figure 13. non burst read transfer basic burst read transfer the pcnet pci ii controller supports burst mode for all bus master read operations. the burst mode must be enabled by setting breade (bcr18, bit 6). to allow burst transfers in descriptor read operations, the pcnet pci ii controller must also be programmed to use swstyle three (bcr20, bits 7-0). all burst read accesses to the initialization block and descriptor ring are of the pci command type memory read (type 6). burst read accesses to the transmit buffer typically are longer than two data phases. when memcmd (bcr18, bit 9) is cleared to zero, all burst read accesses to the transmit buffer are of the pci command type memory read line (type 14). when memcmd (bcr18, bit 9) is set to one, all burst read accesses to the transmit buffer are of the pci command type memory read multiple (type 12). ad[1:0] will both be zero during the address phase indicating a linear burst order. note that during a burst read operation, all byte lanes will always be active. the pcnet pci ii controller will internally discard unneeded bytes. the pcnet pci ii controller will always perform only a single burst read transaction per bus mastership period, where transaction is defined as one address phase and one or multiple data phases. the pcnet pci ii controller supports zero wait state read cycles. it asserts irdy im- mediately after the address phase and at the same time starts sampling devsel . frame is deasserted when the next to last data phase is completed. p r e l i m i n a r y amd 45 AM79C970A the following figure shows a typical burst read access. the pcnet pci ii controller arbitrates for the bus, is granted access, and reads three 32 bit words (dword) from the system memory and then releases the bus. in the example, the memory system extends the data phase of the each access by one wait state. the exam ple assumes that extreq (bcr18, bit 8) is cleared to zero, therefore, req is deasserted in the same cycle as frame is asserted. 19436a-17 frame clk ad irdy trdy c/ be devsel req gnt par devsel is sampled addr 0000 0110 par 1 2345678 10 9 11 data data data par par par figure 14. burst read transfer (extreq = 0, memcmd = 0) basic non burst write transfer by default, the pcnet pci ii controller uses non burst cycles in all bus master write operations. all pcnet pci ii controller non burst write accesses are of the pci command type memory write (type 7). the byte enable signals indicate the byte lanes that have valid data. the pcnet pci ii controller typically performs more than one non burst write transactions within a single bus mastership period. frame is dropped between consecutive non-burst write cycles. req however stays asserted until frame is asserted for the last transac- tion. the pcnet-pci ii controller supports zero wait state write cycles except with the case of descriptor write transfers. (see the section descriptor dma transfers for the only exception.) it asserts irdy im- mediately after the address phase and at the same time starts sampling devsel . amd p r e l i m i n a r y 46 AM79C970A the following figure shows two non burst write transac tions. the first transaction has two wait states. the tar get inserts one wait state by asserting devsel one clock late and another wait state by also asserting trdy one clock late. the second transaction shows a zero wait state write cycle. the target asserts devsel and trdy in the same cycle as the pcnet-pci ii controller asserts irdy . 19436a-18 frame clk ad irdy trdy c/ be devsel req gnt par devsel is sampled addr 0111 par 1 2345678 10 9 data addr data par par par be 0111 be figure 15. non burst write transfer basic burst write transfer the pcnet pci ii controller supports burst mode for all bus master write operations. the burst mode must be enabled by setting bwrite (bcr18, bit 5). to allow burst transfers in descriptor write operations, the pcnet pci ii controller must also be programmed to use swstyle three (bcr20, bits 7-0). all pcnet pci ii controller burst write transfers are of the pci command type memory write (type 7). ad[1:0] will both be zero during the address phase indicating a linear burst order. the byte enable signals indicate the byte lanes that have valid data. the pcnet pci ii controller will always perform a single burst write transaction per bus mastership period, where transaction is defined as one address phase and one or multiple data phases. the pcnet pci ii controller supports zero wait state write cycles except with the case of descriptor write transfers. (see the section descriptor dma transfers" for the only exception.) it asserts irdy immediately after the address phase and at the same time starts sampling devsel . frame is deasserted when the next to the last data phase is completed. p r e l i m i n a r y amd 47 AM79C970A the following figure shows a typical burst write access. the pcnet pci ii controller arbitrates for the bus, is granted access, and writes four 32 bit words (dwords) to the system memory and then releases the bus. in this example, the memory system extends the data phase of the first access by one wait state. the following three data phases take one clock cycle each, which is deter mined by the timing of trdy . the example assumes that extreq (bcr18, bit 8) is set to one, therefore, req is not deasserted until the next to last data phase is finished. 19436a-19 frame clk ad irdy trdy c/ be devsel req gnt 12345678 addr data data data be 0111 9 par par par par par data par devsel is sampled figure 16. burst write transfer (extreq = 1) amd p r e l i m i n a r y 48 AM79C970A target initiated termination when the pcnet pci ii controller is a bus master, the cycles it produces on the pci bus may be terminated by the target in one of three different ways. disconnect with data transfer the figure below shows a disconnection in which one last data transfer occurs after the target asserted stop . stop is asserted on clock 4 to start the termination sequence. data is still transferred during this cycle, since both irdy and trdy are asserted. the pcnet-pci ii controller terminates the current transfer with the deassertion of frame on clock 5 and of irdy one clock later. it finally releases the bus on clock 6. the pcnet-pci ii controller will re-request the bus after 2 clock cycles, if it wants to transfer more data. the start- ing address of the new transfer will be the address of the next untransferred data. 19436a-20 frame clk ad irdy trdy c/ be devsel req gnt par devsel is sampled addr i 0000 0111 par 0111 1 2345678 10 9 par data stop addr i +8 data figure 17. disconnect with data transfer p r e l i m i n a r y amd 49 AM79C970A disconnect without data transfer the figure below shows a target disconnect sequence during which no data is transferred. stop is asserted on clock 4 without trdy being asserted at the same time. the pcnet-pci ii controller terminates the access with the deassertion of frame on clock 5 and of irdy one clock cycle later. it finally releases the bus on clock 6. the pcnet-pci ii controller will re-request the bus after 2 clock cycles to retry the last transfer. the starting address of the new transfer will be the address of the last untransferred data. 19436a-21 frame clk ad irdy trdy c/ be devsel req gnt par devsel is sampled addr i 0000 0111 par 0111 1 2345678 10 9 stop addr i data par figure 18. disconnect without data transfer amd p r e l i m i n a r y 50 AM79C970A target abort the figure below shows a target abort sequence. the target asserts devsel for one clock. it then deasserts devsel and asserts stop on clock 4. a target can use the target abort sequence to indicate that it cannot serv- ice the data transfer and that it does not want the transaction to be retried. additionally, the pcnet-pci ii controller cannot make any assumption about the suc- cess of the previous data transfers in the current trans- action. the pcnet-pci ii controller terminates the current transfer with the deassertion of frame on clock 5 and of irdy one clock cycle later. it finally releases the bus on clock 6. since data integrity is not guaranteed, the pcnet-pci ii controller cannot recover from a target abort event. the pcnet-pci ii controller will reset all csr locations to their stop_reset values. the bcr and pci configuration registers will not be cleared. any on-going network transmission is terminated in an orderly se- quence. if less than 512 bits have been transmitted onto the network, the transmission will be terminated imme- diately, generating a runt packet. if 512 bits or more have been transmitted, the message will have the cur- rent fcs inverted and appended at the next byte bound- ary to guarantee an fcs error is detected at the receiving station. rtabort (pci status register, bit 12) will be set to indi- cate that the pcnet-pci ii controller has received a tar- get abort. in addition, sint (csr5, bit 11) will be set to one. when sint is set, inta is asserted if the enable bit sinte (csr5, bit 10) is set to one. this mechanism can be used to inform the driver of the system error. the host can read the pci status register to determine the exact cause of the interrupt. 19436a-22 frame clk ad irdy trdy c/ be devsel req gnt 1 23456 addr 0000 0111 par par par data devsel is sampled stop figure 19. target abort p r e l i m i n a r y amd 51 AM79C970A master initiated termination there are three scenarios besides normal completion of a transaction where the pcnet pci ii controller will ter minate the cycles it produces on the pci bus. preemption during non burst transaction when the pcnet pci ii controller performs multiple non burst transactions, it keeps req asserted until the assertion of frame for the last transaction. when gnt is removed, the pcnet-pci ii controller will finish the current transaction and then release the bus. if it is not the last transaction, req will remain asserted to regain bus ownership as soon as possible. 19436a-23 frame clk ad irdy trdy c/ be devsel req gnt 1 234567 be 0111 par par devsel is sampled par data addr figure 20. preemption during non burst transaction amd p r e l i m i n a r y 52 AM79C970A preemption during burst transaction when the pcnet pci ii controller operates in burst mode, it only performs a single transaction per bus mas tership period, where transaction is defined as one ad dress phase and one or multiple data phases. the central arbiter can remove gnt at any time during the transaction. the pcnet-pci ii controller will ignore the deassertion of gnt and continue with data transfers, as long as the pci latency timer is not expired. when the latency timer is zero and gnt is deasserted, the pcnet-pci ii controller will finish the current data phase, deassert frame , finish the last data phase and release the bus. if extreq (bcr18, bit 8) is cleared to zero, it will immediately assert req to regain bus ownership as soon as possible. if extreq is set to one, req will stay asserted. when the preemption occurs after the counter has counted down to zero, the pcnet-pci ii controller will finish the current data phase, deassert frame , finish the last data phase and release the bus. note that it is important for the host to program the pci latency timer according to the bus bandwidth require- ment of the pcnet-pci ii controller. the host can deter- mine this bus bandwidth requirement by reading the pci max_lat and min_gnt registers. the figure below assumes that the pci latency timer has counted down to zero on clock 7. 19436a-24 frame clk ad irdy trdy c/ be devsel par devsel is sampled addr be 0111 par 1 234 5 6 78 9 data par req data data data data par par par par gnt figure 21. preemption during burst transaction p r e l i m i n a r y amd 53 AM79C970A master abort the pcnet pci ii controller will terminate its cycle with a master abort sequence if devsel is not asserted within 4 clocks after frame is asserted. master abort is treated as a fatal error by the pcnet-pci ii controller. the pcnet-pci ii controller will reset all csr locations to their stop_reset values. the bcr and pci con- figuration registers will not be cleared. any on-going net- work transmission is terminated in an orderly sequence. if less than 512 bits have been transmitted onto the net- work, the transmission will be terminated immediately, generating a runt packet. if 512 bits or more have been transmitted, the message will have the current fcs inverted and appended at the next byte boundary to guarantee an fcs error is detected at the receiving station. rmabort (in the pci status register, bit 13) will be set to indicate that the pcnet-pci ii controller has termi- nated its transaction with a master abort. in addition, sint (csr5, bit 11) will be set to one. when sint is set, inta is asserted if the enable bit sinte (csr5, bit 10) is set to one. this mechanism can be used to in- form the driver of the system error. the host can read the pci status register to determine the exact cause of the interrupt. 19436a-25 frame clk ad irdy trdy c/ be devsel par devsel is sampled addr 0111 par 1 234 5 6 78 9 data par req gnt 0000 figure 22. master abort amd p r e l i m i n a r y 54 AM79C970A parity error response during every data phase of a dma read operation, when the target indicates that the data is valid by asserting trdy , the pcnet-pci ii controller samples the ad[31:0], c/ be [3:0] and the par lines for a data parity error. when it detects a data parity error, the controller sets perr (pci status register, bit 15) to one. when reporting of that error is enabled by setting perren (pci command register, bit 6) to one, the pcnet-pci ii controller also drives the perr signal low and sets dataperr (pci status register, bit 8) to one. the assertion of perr follows the corrupted data/byte en- ables by two clock cycles and par by one clock cycle. the figure below shows a transaction that has a parity error in the data phase. the pcnet-pci ii controller as- serts perr on clock 8, two clock cycles after data is valid. the data on clock 5 is not checked for parity, since on a read access par is only required to be valid one clock after the target has asserted trdy . the pcnet-pci ii controller then drives perr high for one clock cycle, since perr is a sustained tri-state signal. 19436a-26 frame clk ad irdy trdy c/ be devsel par devsel is sampled addr be 0111 par 1 234 5 6 78 9 data par perr figure 23. master cycle data parity error response during every data phase of a dma write operation, the pcnet pci ii controller checks the perr input to see if the target reports a parity error. when it sees the perr input asserted, the controller sets perr (pci status register, bit 15) to one. when perren (pci com- mand register, bit 6) is set to one, the pcnet-pci ii con- troller also sets dataperr (pci status register, bit 8) to one. whenever the pcnet-pci ii controller is the current bus master and a data parity error occurs, sint (csr5, bit 11) will be set to one. when sint is set, inta is as- serted if the enable bit sinte (csr5, bit 10) is set to one. this mechanism can be used to inform the driver of the system error. the host can read the pci status register to determine the exact cause of the interrupt. the setting of sint due to a data parity error is not de- pendent on the setting of perren (pci command register, bit 6). by default, a data parity error does not affect the state of the mac engine. the pcnet-pci ii controller treats the data in all bus master transfers that have a parity p r e l i m i n a r y amd 55 AM79C970A error as if nothing has happened. all network activity continues. advanced parity error handling for all dma cycles, the pcnet pci ii controller provides a second, more advanced level of parity error handling. this mode is enabled by setting aperren (bcr20, bit 10) to one. when aperren is set to one, the bpe bits (rmd1 and tmd1, bit 23) are used to indicate parity error in data transfers to the receive and transmit buffers. note that since the advanced parity error handling uses an additional bit in the descriptor, swstyle (bcr20, bits 7-0) must be set to one, two or three to program the pcnet pci ii controller to use 32 bit software structures. the pcnet pci ii controller will react in the following way when a data parity error occurs: n initialization block read: stop (csr0, bit 2) is set to one and causes a stop_reset of the device. n descriptor ring read: any on going network activity is terminated in an orderly sequence and then stop (csr0, bit 2) is set to one to cause a stop_reset of the device. n descriptor ring write: any on going network activity is terminated in an orderly sequence and then stop (csr0, bit 2) is set to one to cause a stop_reset of the device. n transmit buffer read: bpe (tmd1, bit 23) is set in the current transmit descriptor. any on going network transmission is terminated in an orderly sequence. n receive buffer write: bpe (rmd1, bit 23) is set in the last receive descriptor associated with the frame. terminating on going network transmission in an or derly sequence means that if less than 512 bits have been transmitted onto the network, the transmission will be terminated immediately, generating a runt packet. if 512 bits or more have been transmitted, the message will have the current fcs inverted and appended at the next byte boundary to guarantee an fcs error is de tected at the receiving station. aperren does not affect the reporting of address par ity errors or data parity errors that occur when the pcnet pci ii controller is the target of the transfer. amd p r e l i m i n a r y 56 AM79C970A initialization block dma transfers during execution of the pcnet pci ii controller bus master initialization procedure, the pcnet pci ii con troller microcode will repeatedly request dma transfers from the biu. during each of these initialization block dma transfers, the biu will perform two data transfer cy cles reading one dword per transfer and then it will re linquish the bus. when ssize32 (bcr20, bit 8) is set to one (i.e. the initialization block is organized as 32 bit software structures), there are 7 dwords to transfer dur ing the bus master initialization procedure, so four bus mastership periods are needed in order to complete the initialization sequence. note that the last dword trans fer of the last bus mastership period of the initialization sequence accesses an unneeded location. data from this transfer is discarded internally. when ssize32 is cleared to zero (i.e. the initialization block is organized as 16 bit software structures), then three bus mastership periods are needed to complete the initialization sequence. the pcnet pci ii controller supports two transfer modes for reading the initialization block: non burst and burst mode; with burst mode being the preferred mode when the pcnet pci ii controller is used in a pci bus application. when breade is cleared to zero (bcr18, bit 6), all initialization block read transfers will be executed in non burst mode. there is a new address phase for every data phase. frame will be dropped between the two transfers. the two phases within a bus mastership period will have addresses of ascending contiguous order. 19436a-27 frame clk ad irdy trdy c/ be devsel req gnt par devsel is sampled iadd i 0000 0110 par par data data iadd i +4 0000 0110 par par 1 2345678 10 9 figure 24. initialization block read in non burst mode p r e l i m i n a r y amd 57 AM79C970A when breade is set to one (bcr18, bit 6), all initiali zation block read transfers will be executed in burst mode. ad[1:0] will be zero during the address phase indicating a linear burst order. 19436a 28 frame clk ad irdy trdy c/ be devsel req gnt 1 234567 0000 0110 par par par par devsel is sampled data data iadd i figure 25. initialization block read in burst mode amd p r e l i m i n a r y 58 AM79C970A descriptor dma transfers pcnet pci ii controller microcode will determine when a descriptor access is required. a descriptor dma read will consist of two data transfers. a descriptor dma write will consist of one or two data transfers. the descriptor dma transfers within a single bus mastership period will always be of the same type (either all read or all write). during descriptor read accesses, the byte enable sig nals will indicate that all byte lanes are active. should some of the bytes not be needed, then the pcnet pci ii controller will internally discard the extraneous informa tion that was gathered during such a read. the settings of swstyle (bcr20, bits 7-0) and breade (bcr18, bit 6) affect the way the pcnet pci ii controller performs descriptor read operations. when swstyle is set to zero, one or two, all descriptor read operations are performed in non burst mode. the setting of breade has no effect in this configuration. when swstyle is set to three, the descriptor entries are ordered to allow burst transfers. the pcnet pci ii controller will perform all descriptor read operations in burst mode, if breade is set to one. table 4. descriptor read sequence swstyle breade bcr18[6] bcr20[7:0] ad bus sequence 0 x address = xxxx xx00h turn around cycle data = md1[31:24], md0[23:0] idle address = xxxx xx04h turn around cycle data = md2[15:0], md1[15:0] 1,2 x address = xxxx xx04h turn around cycle data = md1[31:0] idle address = xxxx xx00h turn around cycle data = md0[31:0] 3 0 address = xxxx xx04h turn around cycle data = md1[31:0] idle address = xxxx xx08h turn around cycle data = md0[31:0] 3 1 address = xxxx xx04h turn around cycle data = md1[31:0] data = md0[31:0] p r e l i m i n a r y amd 59 AM79C970A 19436a 29 frame clk ad irdy trdy c/ be devsel req gnt par devsel is sampled md1 0000 0110 par par data data md0 0000 0110 par par 1 2345678 10 9 figure 26. descriptor ring read in non burst mode during descriptor write accesses, only the byte lanes which need to be written are enabled. if buffer chaining is used, accesses to the descriptors of all intermediate buffers consist of only one data transfer to return ownership of the buffer to the system. when swstyle (bcr20, bits 7-0) is cleared to zero (i.e. the descriptor entries are organized as 16 bit software structures), the descriptor access will write a single byte. when swstyle (bcr20, bits 7-0) is set to one, two or three (i.e. the descriptor entries are organized as 32 bit software structures), the descriptor access will write a single word. on all single buffer transmit or re ceive descriptors, as well as on the last buffer in chain, writes to the descriptor consist of two data transfers. the first one writing a dword containing status information. the second data transfer writing a byte (swstyle cleared to zero) or otherwise a word containing addi tional status and the ownership bit (i.e. md1[31]). amd p r e l i m i n a r y 60 AM79C970A 19436a 30 frame clk ad irdy trdy c/ be devsel req gnt 1 234567 md1 0000 0110 par par par data data par devsel is sampled figure 27. descriptor ring read in burst mode the settings of swstyle (bcr20, bits 7-0) and bwrite (bcr18, bit 5) affect the way the pcnet pci ii controller performs descriptor write operations. when swstyle is set to zero, one or two, all descriptor write operations are performed in non burst mode. the setting of bwrite has no effect in this configuration. when swstyle is set to three, the descriptor entries are ordered to allow burst transfers. the pcnet pci ii controller will perform all descriptor write operations in burst mode, if bwrite is set to one. a write transaction to the descriptor ring entries is the only case where the pcnet pci ii controller inserts a wait state when being the bus master. every data phase in non burst and burst mode is extended by one clock cycle, during which irdy is deasserted. table 5. descriptor write sequence swstyle bwrite bcr20[7:0] bcr18[5] ad bus sequence 0 x address = xxxx xx04h data = md2[15:0], md1[15:0] idle address = xxxx xx00h data = md1[31:24] 1,2 x address = xxxx xx08h data = md2[31:0] idle address = xxxx xx04h data = md1[31:16] 3 0 address = xxxx xx00h data = md2[31:0] idle address = xxxx xx04h data = md1[31:16] 3 1 address = xxxx xx00h data = md2[31:0] data = md1[31:16] p r e l i m i n a r y amd 61 AM79C970A note that the figure below assumes that the pcnet pci ii controller is programmed to use 32 bit software structures (swstyle = 1, 2, or 3). the byte enable signals for the second data transfer would be 0111b, if the device was programmed to use 16 bit soft ware structures (swstyle = 0). 19436a 31 frame clk ad irdy trdy c/ be devsel req gnt par devsel is sampled md2 0000 0111 par md1 0011 0111 par 1 2345678 10 9 data par par data figure 28. descriptor ring write in non burst mode amd p r e l i m i n a r y 62 AM79C970A 19436a 32 gnt req devsel trdy par c/ be frame clk 35 par ad irdy devsel is sampled data 1 2 4 6 7 8 0110 0000 0011 md2 par data par figure 29. descriptor ring write in burst mode fifo dma transfers pcnet pci ii controller microcode will determine when a fifo dma transfer is required. this transfer mode will be used for transfers of data to and from the pcnet pci ii controller fifos. once the pcnet pci ii controller biu has been granted bus mastership, it will perform a series of consecutive transfer cycles before relinquishing the bus. all transfers within the master cy cle will be either read or write cycles, and all transfers will be to contiguous, ascending addresses. both non burst and burst cycles are used, with burst mode being the preferred mode when the device is used in a pci bus application. non burst fifo dma transfers in the default mode the pcnet pci ii controller uses non burst transfers to read and write data when accessing the fifos. each non burst transfer will be performed sequentially, with the issue of an address, and the transfer of the corresponding data with appropri ate output signals to indicate selection of the active data bytes during the transfer. frame will be deasserted after every address phase. the number of data transfer cycles contained within a single bus mastership period is in general dependent on the programming of the dmaplus option (csr4, bit 14). several other factors will also affect the length of the bus mastership period. the possibilities are as follows: if dmaplus is cleared to zero, a maximum of 16 transfers will be performed by default. this default value may be changed by writing to the dma transfer counter (csr80). note that dmaplus = 0 merely sets a maximum value. the minimum number of transfers in the bus mastership period will be determined by all of the following variables: the settings of the fifo water- marks (csr80), the conditions of the fifos, the value of the dma transfer counter (csr80), the value of the dma bus timer (csr82), and any occurrence of preemption that takes place during the bus mastership period. if dmaplus is set to one, bus cycles will continue until the transmit fifo is filled to its high threshold (read transfers) or the receive fifo is emptied to its low p r e l i m i n a r y amd 63 AM79C970A threshold (write transfers), or until the dma bus activity timer (csr82) has expired. the exact number of total transfer cycles in the bus mastership period is depend ent on all of the following variables: the settings of the fifo watermarks, the conditions of the fifos, the latency of the system bus to the pcnet pci ii controller's bus request, the speed of bus operation and bus preemption events. the dma transfer counter is disabled when dmaplus is set to one. the trdy re- sponse time of the memory device will also affect the number of transfers, since the speed of the accesses will affect the state of the fifo. during accesses, the fifo may be filling or emptying on the network end. for example, on a receive operation, a slower trdy re- sponse will allow additional data to accumulate inside of the fifo. if the accesses are slow enough, a complete dword may become available before the end of the bus mastership period and thereby increase the number of transfers in that period. the general rule is that the longer the bus grant latency, the slower the bus transfer operations, the slower the clock speed, the higher the transmit watermark or the lower the receive watermark, the longer the bus mastership period will be. note that the pci latency timer is not significant during non-burst transfers. burst fifo dma transfers bursting is only performed by the pcnet-pci ii controller if the breade and/or bwrite bits of bcr18 are set. these bits individually enable/disable the ability of the pcnet-pci ii controller to perform burst accesses during master read operations and master write operations, respectively. a burst transaction will start with an address phase, fol- lowed by one or more data phases. ad[1:0] will always be zero during the address phase indicating a linear burst order. during fifo dma read operations, all byte lanes will al- ways be active. the pcnet-pci ii controller will inter- nally discard unused bytes. during the first and the last data phases of a fifo dma burst write operation, one or more of the byte enable signals may be inactive. all other data phases will always write a complete dword. amd p r e l i m i n a r y 64 AM79C970A the following figure shows the beginning of a fifo dma write with the beginning of the buffer not aligned to a dword boundary. the pcnet pci ii controller starts off by writing only three bytes during the first data phase. this operation aligns the address for all other data trans fers to a 32 bit boundary so that the pcnet pci ii con troller can continue bursting full dwords. 19436a 33 frame clk ad irdy trdy c/ be devsel req gnt 1 23456 0000 0111 par par par devsel is sampled 0001 par data data data add figure 30. fifo burst write at start of unaligned buffer p r e l i m i n a r y amd 65 AM79C970A if a receive buffer does not end on a dword boundary, the pcnet pci ii controller will perform a non dword write on the last transfer to the buffer. the following fig ure shows the final three fifo dma transfers to a re ceive buffer. since there were only nine bytes of space left in the receive buffer, the pcnet pci ii controller burst three data phases. the first two data phases write a full dword, the last one only writes a single byte. note that the pcnet pci ii controller will always perform a dword transfer as long as it owns the buffer space, even when there are less then four bytes to write. for ex ample, if there is only one byte left for the current receive frame, the pcnet pci ii controller will write a full dword, containing the last byte of the receive frame in the least significant byte position (bswp is cleared to zero, csr3, bit 2). the content of the other three bytes is undefined. the message byte count in the receive descriptor always reflects the exact length of the received frame. 19436a 34 frame clk ad irdy trdy c/ be devsel req gnt 1 234567 0000 0111 par par par par devsel is sampled 1110 par data data data add figure 31. fifo burst write at end of unaligned buffer in a pci bus application the pcnet pci ii controller should be set up to have the length of a bus mastership period be controlled only by the pci latency timer. the timer bit (csr4, bit 13) should remain at its default value of zero so that the dma bus activity timer (csr82) is not enabled. the dma transfer counter (csr80) should be disabled by setting dmaplus (csr4, bit 14) to one. in this mode, the pcnet pci ii controller will continue transferring fifo data until the transmit fifo is filled to its high threshold (read trans fers) or the receive fifo is emptied to its low threshold (write transfers), or the pcnet pci ii controller is preempted, and the pci latency timer is expired. the host should use the values in the pci min_gnt and max_lat registers to determine the value for the pci latency timer. amd p r e l i m i n a r y 66 AM79C970A in applications that don't use the pci latency timer or that don't support preemption the following rules apply to limit the time the pcnet pci ii controller takes up on the bus. if dmaplus is cleared to zero, a maximum of 16 transfers will be performed by default. this default value may be changed by writing to the dma transfer counter (csr80). note that dmaplus = 0 merely sets a maxi mum value. the minimum number of transfers in the bus mastership period will be determined by all of the follow ing variables: the settings of the fifo watermarks (csr80), the conditions of the fifos, the value of the dma transfer counter (csr80) and the value of the dma bus activity timer (csr82). if dmaplus is set to one, bursting will continue until the transmit fifo is filled to its high threshold (read transfers) or the receive fifo is emptied to its low threshold (write transfers), or until the dma bus activity timer (csr82) has expired. the exact number of total transfer cycles in the bus mastership period is dependent on all of the following variables: the settings of the fifo watermarks, the conditions of the fifos, the latency of the system bus to the pcnet pci ii controller's bus request, and the speed of bus operation. the dma transfer counter is disabled when dmaplus is set to one. the trdy response time of the memory device will also affect the number of transfers, since the speed of the accesses will affect the state of the fifo. during accesses, the fifo may be filling or emptying on the network end. for example, on a receive operation, a slower trdy response will allow additional data to ac- cumulate inside of the fifo. if the accesses are slow enough, a complete dword may become available be- fore the end of the bus mastership period and thereby increase the number of transfers in that period. the gen- eral rule is that the longer the bus grant latency, the slower the bus transfer operations, the slower the clock speed, the higher the transmit watermark or the lower the receive watermark, the longer the total burst length will be. when a fifo dma burst operation is preempted, the pcnet-pci ii controller will not relinquish bus ownership until the pci latency timer expires. the dma transfer counter will freeze at the current value while the pcnet-pci ii controller is waiting to regain bus owner- ship. it will continue counting when the fifo dma burst operation restarts. the bus activity timer will be reset to its starting value when the pcnet-pci ii controller re- gains bus ownership. the pci latency timer cannot be disabled. systems that support preemption and that want to control the duration of the pcnet-pci ii controller bus mastership period with the dma transfer counter or the bus activity timer must program the pci latency timer with a high value so that it does not expire before the other two registers do. buffer management unit the buffer management unit (bmu) is a microcoded state machine which implements the initialization proce- dure and manages the descriptors and buffers. the buffer management unit operates at half the speed of the clk input. initialization pcnet-pci ii controller initialization includes the reading of the initialization block in memory to obtain the operat- ing parameters. the initialization block can be organ- ized in two ways. when ssize32 (bcr20, bit 8) is at its default value of zero, all initialization block entries are logically 16-bits wide to be backwards compatible with the am79c90 c-lance and am79c96x pcnet-isa family. when ssize32 (bcr20, bit 8) is set to one, all initialization block entries are logically 32-bits wide. note that the pcnet-pci ii controller always performs 32-bit bus transfers to read the initialization block en- tries. the initialization block is read when the init bit in csr0 is set. the init bit should be set before or concur- rent with the strt bit to insure correct operation. once the initialization block has been completely read in and internal registers have been updated, idon will be set in csr0, generating an interrupt (if iena is set). the pcnet-pci ii controller obtains the start address of the initialization block from the contents of csr1 (least significant 16 bits of address) and csr2 (most signifi- cant 16 bits of address). the host must write csr1 and csr2 before setting the init bit. the initialization block contains the user defined conditions for pcnet-pci ii controller operation, together with the base addresses and length information of the transmit and receive descriptor rings. there is an alternate method to initialize the pcnet-pci ii controller. instead of initialization via the initialization block in memory, data can be written directly into the ap- propriate registers. either method or a combination of the two may be used at the discretion of the programmer. please refer to appendix c for details on this alternate method. re-initialization the transmitter and receiver sections of the pcnet-pci ii controller can be turned on via the initialization block (dtx, drx, csr15, bits 1C0). the states of the trans- mitter and receiver are monitored by the host through csr0 (rxon, txon bits). the pcnet-pci ii controller should be re-initialized if the transmitter and/or the re- ceiver were not turned on during the original initializa- tion, and it was subsequently required to activate them or if either section was shut off due to the detection of an error condition (merr, uflo, tx buff error). re-initialization may be done via the initialization block or by setting the stop bit in csr0, followed by writing p r e l i m i n a r y amd 67 AM79C970A to csr15, and then setting the start bit in csr0. note that this form of restart will not perform the same in the pcnet pci ii controller as in the clance. in par ticular, upon restart, the pcnet pci ii controller reloads the transmit and receive descriptor pointers with their respective base addresses. this means that the soft ware must clear the descriptor own bits and reset its descriptor ring pointers before restarting the pcnet pci ii controller. the reload of descriptor base addresses is performed in the clance only after initialization, so a restart of the clance without initialization leaves the clance pointing at the same descriptor locations as before the restart. suspend the pcnet pci ii controller offers a suspend mode that allows easy updating of the csr registers without going through a full re initialization of the device. the suspend mode also allows stopping the device with orderly termi nation of all network activity. the host requests the pcnet pci ii controller to enter the suspend mode by setting spnd (csr5, bit 0) to one. when the host sets spnd to one, the pcnet pci ii controller first finishes all on going trans mit activity and updates the corresponding transmit de scriptor entries. it then finishes all on going receive activity and updates the corresponding receive descrip tor entries. it then sets the read version of spnd to one and enters the suspend mode. the host must poll spnd until it reads back one to determine that the pcnet pci ii controller has entered the suspend mode. in suspend mode, all of the csr and bcr registers are accessible. as long as the pcnet pci ii controller is not reset while in suspend mode (by h_reset, s_reset or by set ting the stop bit), no re initialization of the device is re quired after the device comes out of suspend mode. when the host clears spnd, the pcnet pci ii controller will leave the suspend mode and will continue at the transmit and receive descriptor ring locations, where it had left off. buffer management buffer management is accomplished through message descriptor entries organized as ring structures in memory. there are two descriptor rings, one for transmit and one for receive. each descriptor describes a single buffer. a frame may occupy one or more buff ers. if multiple buffers are used, this is referred to as buffer chaining. descriptor rings each descriptor ring must occupy a contiguous area of memory. during initialization the user defined base ad dress for the transmit and receive descriptor rings, as well as the number of entries contained in the descriptor rings are set up. the programming of the software style (swstyle, bcr20, bits 7-0) affects the way the de scriptor rings and their entries are arranged. when swstyle is at its default value of zero, the de scriptor rings are backwards compatible with the am79c90 c lance and am79c96x pcnet isa family. the descriptor ring base addresses must be aligned to an 8 byte boundary and a maximum of 128 ring entries is allowed when the ring length is set through the tlen and rlen fields of the initialization block. each ring entry contains a subset of the three 32 bit transmit or re ceive message descriptors (tmd, rmd) that are organ ized as four 16 bit structures (ssize (bcr20, bit 8) is set to zero). note that even though the pcnet pci ii controller treats the descriptor entries as 16 bit struc tures, it will always perform 32 bit bus transfers to ac cess the descriptor entries. the value of csr2, bits 15-8 is used as the upper 8 bits for all memory ad dresses during bus master transfers. when swstyle is set to one, two or three, the descriptor ring base addresses must be aligned to a 16 byte boundary and a maximum of 512 ring entries is allowed when the ring length is set through the tlen and rlen fields of the initialization block. each ring en try is organized as three 32 bit message descriptors (ssize32 (bcr20, bit 8) is set to one). the fourth dword is reserved. when swstyle is set to three, the order of the message descriptors is optimized to al low read and write access in burst mode. for any software style, the ring lengths can be set be yond this range (up to 65535) by writing the transmit and receive ring length registers (csr76, csr78) directly. each ring entry contains the following information: n the address of the actual message data buffer in user or host memory n the length of the message buffer n status information indicating the condition of the buffer to permit the queuing and de queuing of message buff ers, ownership of each buffer is allocated to either the pcnet pci ii controller or the host. the own bit within the descriptor status information, either tmd or rmd, is used for this purpose. when own is set to one, it signi fies that the pcnet pci ii controller currently has owner ship of this ring descriptor and its associated buffer. only the owner is permitted to relinquish ownership or to write to any field in the descriptor entry. a device that is not the current owner of a descriptor entry cannot as sume ownership or change any field in the entry. a device may, however, read from a descriptor that it does not currently own. software should always read descrip tor entries in sequential order. when software finds that the current descriptor is owned by the pcnet pci ii amd p r e l i m i n a r y 68 AM79C970A controller, then the software must not read ahead to the next descriptor. the software should wait at a descriptor it does not own until the pcnet pci ii controller sets own to zero to release ownership to the software. (when lappen (csr3, bit 5) is set to one, this rule is modified. see the lappen description.) at initialization, the pcnet pci ii controller reads the base address of both the transmit and receive descriptor rings into csrs for use by the pcnet pci ii controller during subsequent operations. the following figure illustrates the relationship between the initialization base address, the initialization block, the receive and transmit descriptor ring base ad dresses, the receive and transmit descriptors and the receive and transmit data buffers, when ssize32 is cleared to zero. note that the value of csr2, bits 15-8 is used as the upper 8 bits for all memory addresses during bus master transfers. 19436a 35 initialization block iadr[15:0] iadr[31:16] csr1 csr2 tdra[15:0] mod padr[15:0] padr[31:16] padr[47:32] ladrf[15:0] ladrf[31:16] ladrf[47:32] ladrf[63:48] rdra[15:0] rle res rdra[23:16] tle res tdra[23:16] rcv buffers rmd0 rmd rmd rmd rcv descriptor ring n n n n 1st desc. start 2nd desc. rmd0 xmt buffers tmd tmd tmd tmd xmt descriptor ring m m m m 1st desc. start 2nd desc. tmd data buffer n data buffer 1 data buffer 2 data buffer m data buffer 1 data buffer 2 figure 32. 16 bit software model p r e l i m i n a r y amd 69 AM79C970A the following figure illustrates the relationship between the initialization base address, the initialization block, the receive and transmit descriptor ring base addresses, the receive and transmit descriptors and the receive and transmit data buffers, when ssize32 is set to one. 19436a 36 initialization block csr1 csr2 rcv buff rmd rmd rmd rmd rcv descriptor ring n n n n 1st desc. start 2nd desc. start rmd xmt buff tmd0 tmd1 tmd2 tmd3 xmt descriptor ring m m m m 1st desc. start 2nd desc. start tmd0 data buffer n data buffer 1 data buffer 2 data buffer m data buffer 2 data buffer 1 padr[31:0] iadr[31:16] iadr[15:0] tle res rle res mode padr[47:32] res ladrf[31:0] ladrf[63:32] rdra[31:0] tdra[31:0] figure 33. 32 bit software model polling if there is no network channel activity and there is no pre or post receive or pre or post transmit activity be ing performed by the pcnet pci ii controller, then the pcnet pci ii controller will periodically poll the current receive and transmit descriptor entries in order to ascer tain their ownership. if the dpoll bit in csr4 is set, then the transmit polling function is disabled. a typical polling operation consists of the following: the pcnet pci ii controller will use the current receive de scriptor address stored internally to vector to the appropriate receive descriptor table entry (rdte). it will then use the current transmit descriptor address (stored internally) to vector to the appropriate transmit descriptor table entry (tdte). the accesses will be made in the following order: rmd1, then rmd0 of the current rdte during one bus arbitration, and after that, tmd1, then tmd0 of the current tdte during a second bus arbitration. all information collected during polling activity will be stored internally in the appropriate csrs, if the own bit is set. (i.e. csr18, csr19, csr20, csr21, csr40, csr42, csr50, csr52). amd p r e l i m i n a r y 70 AM79C970A a typical receive poll is the product of the following conditions: 1. pcnet pci ii controller does not own the current dte and the poll time has elapsed and rxon = 1 (csr0, bit 5), or 2. pcnet pci ii controller does not own the next rdte and there is more than one receive descriptor in the ring and the poll time has elapsed and rxon = 1. if rxon is cleared to zero, the pcnet pci ii controller will never poll rdte locations. in order to avoid missing frames the system should have at least on rdte available. to minimize poll activity two rdtes should be available. in this case, the poll opera tion will only consist of the check of the status of the current tdte. a typical transmit poll is the product of the following conditions: 1. pcnet pci ii controller does not own the current tdte and dpoll = 0 (csr4, bit 12) and txon = 1 (csr0, bit 4) and the poll time has elapsed, or 2. pcnet pci ii controller does not own the current tdte and dpoll = 0 and txon = 1 and a frame has just been received, or 3. pcnet pci ii controller does not own the current tdte and dpoll = 0 and txon = 1 and a frame has just been transmitted. setting the tdmd bit of csr0 will cause the microcode controller to exit the poll counting code and immediately perform a polling operation. if rdte ownership has not been previously established, then an rdte poll will be performed ahead of the tdte poll. if the microcode is not executing the poll counting code when the tdmd bit is set, then the demanded poll of the tdte will be delayed until the microcode returns to the poll counting code. the user may change the poll time value from the de fault of 65,536 clock periods by modifying the value in the polling interval register (csr47). transmit descriptor table entry if, after a transmit descriptor table entry (tdte) ac cess, the pcnet pci ii controller finds that the own bit of that tdte is not set, the pcnet pci ii controller re sumes the poll time count and re examines the same tdte at the next expiration of the poll time count. if the own bit of the tdte is set, but the start of packet (stp) bit is not set, the pcnet pci ii controller will im mediately request the bus in order to clear the own bit of this descriptor. (this condition would normally be found following a late collision (lcol) or retry (rtry) error that occurred in the middle of a transmit frame chain of buffers.) after resetting the own bit of this de scriptor, the pcnet pci ii controller will again immediately request the bus in order to access the next tdte location in the ring. if the own bit is set and the buffer length is 0, the own bit will be cleared. in the c lance the buffer length of 0 is interpreted as a 4096 byte buffer. a zero length buff ers is acceptable as long as it is not the last buffer in a chain (stp = 0 and enp = 1). if the own bit and stp are set, then microcode control proceeds to a routine that will enable transmit data transfers to the fifo. the pcnet pci ii controller will look ahead to the next transmit descriptor after it has performed at least one transmit data transfer from the first buffer. if the pcnet pci ii controller does not own the next tdte (i.e. the second tdte for this frame), it will com plete transmission of the current buffer and update the status of the current (first) tdte with the buff and uflo bits being set. if dxsuflo (csr3, bit 6) is cleared to zero, the underflow error will cause the transmitter to be disabled (csr0, txon = 0). the pcnet pci ii controller will have to be re initialized to re store the transmit function. setting dxsuflo to one enables the pcnet pci ii controller to gracefully recover from an underflow error. the device will scan the trans mit descriptor ring until it finds either the start of a new frame or a tdte it does not own. to avoid an underflow situation in a chained buffer transmission, the system should always set the transmit chain descriptor own bits in reverse order. if the pcnet pci ii controller does own the second tdte in a chain, it will gradually empty the contents of the first buffer (as the bytes are needed by the transmit operation), perform a single cycle dma transfer to up date the status of the first descriptor (clear the own bit in tmd1), and then it may perform one data dma ac cess on the second buffer in the chain before executing another lookahead operation. (i.e. a lookahead to the third descriptor.) it is imperative that the host system never reads the tdte own bits out of order. the pcnet pci ii control ler normally clears own bits in strict fifo order. how ever, the pcnet pci ii controller can queue up to two frames in the transmit fifo. when the second frame uses buffer chaining, the pcnet pci ii controller might return ownership out of normal fifo order. the own bit for last (and maybe only) buffer of the first frame is not cleared until transmission is completed. during the transmission the pcnet pci ii controller will read in buff ers for the next frame and clear their own bits for all but the last one. the first and all intermediate buffers of the second frame can have their own bits cleared before p r e l i m i n a r y amd 71 AM79C970A the pcnet pci ii controller returns ownership for the last buffer of the first frame. if an error occurs in the transmission before all of the bytes of the current buffer have been transferred, trans mit status of the current buffer will be immediately up dated. if the buffer does not contain the end of packet, the pcnet pci ii controller will skip over the rest of the frame which experienced the error. this is done by re turning to the polling microcode where the pcnet pci ii controller will clear the own bit for all descriptors with own = 1 and stp = 0 and continue in like manner until a descriptor with own = 0 (no more transmit frames in the ring) or own = 1 and stp = 1 (the first buffer of a new frame) is reached. at the end of any transmit operation, whether successful or with errors, immediately following the completion of the descriptor updates, the pcnet pci ii controller will always perform another polling operation. as described earlier, this polling operation will begin with a check of the current rdte, unless the pcnet pci ii controller al ready owns that descriptor. then the pcnet pci ii con troller will poll the next tdte. if the transmit descriptor own bit has a zero value, the pcnet pci ii controller will resume incrementing the poll time counter. if the transmit descriptor own bit has a value of one, the pcnet pci ii controller will begin filling the fifo with transmit data and initiate a transmission. this end of operation poll coupled with the tdte lookahead opera tion allows the pcnet pci ii controller to avoid inserting poll time counts between successive transmit frames. by default, whenever the pcnet pci ii controller com pletes a transmit frame (either with or without error) and writes the status information to the current descriptor, then the tint bit of csr0 is set to indicate the comple tion of a transmission. this causes an interrupt signal if the iena bit of csr0 has been set and the tintm bit of csr3 is cleared. the pcnet pci ii controller provides two modes to reduce the number of transmit interrupts. the interrupt of a successfully transmitted frame can be suppressed by setting tintokd (csr5, bit 15) to one. another mode, which is enabled by setting ltinten (csr5, bit 14) to one, allows suppression of interrupts for successful transmissions for all but the last frame in a sequence. receive descriptor table entry if the pcnet pci ii controller does not own both the cur rent and the next receive descriptor table entry (rdte) then the pcnet pci ii controller will continue to poll according to the polling sequence described above. if the receive descriptor ring length is one, then there is no next descriptor to be polled. if a poll operation has revealed that the current and the next rdte belong to the pcnet pci ii controller then additional poll accesses are not necessary. future poll operations will not include rdte accesses as long as the pcnet pci ii controller retains ownership of the cur rent and the next rdte. when receive activity is present on the channel, the pcnet pci ii controller waits for the complete address of the message to arrive. it then decides whether to ac cept or reject the frame based on all active addressing schemes. if the frame is accepted the pcnet pci ii con troller checks the current receive buffer status register crst (csr41) to determine the ownership of the current buffer. if ownership is lacking, the pcnet pci ii controller will immediately perform a final poll of the current rdte. if ownership is still denied, the pcnet pci ii controller has no buffer in which to store the incoming message. the miss bit will be set in csr0 and the missed frame counter (csr112) will be incremented. an interrupt will be generated if iena (csr0, bit 6) is set to one and missm (csr3, bit 12) is cleared to zero. another poll of the current rdte will not occur until the frame has finished. if the pcnet pci ii controller sees that the last poll (either a normal poll, or the final effort described in the above paragraph) of the current rdte shows valid own ership, it proceeds to a poll of the next rdte. following this poll, and regardless of the outcome of this poll, transfers of receive data from the fifo may begin. regardless of ownership of the second receive descriptor, the pcnet pci ii controller will continue to perform receive data dma transfers to the first buffer. if the frame length exceeds the length of the first buffer, and the pcnet pci ii controller does not own the second buffer, ownership of the current descriptor will be passed back to the system by writing a zero to the own bit of rmd1 and status will be written indicating buffer (buff = 1) and possibly overflow (oflo = 1) errors. if the frame length exceeds the length of the first (cur rent) buffer, and the pcnet pci ii controller does own the second (next) buffer, ownership will be passed back to the system by writing a zero to the own bit of rmd1 when the first buffer is full. the own bit is the only bit modified in the descriptor. receive data transfers to the second buffer may occur before the pcnet pci ii controller proceeds to look ahead to the ownership of the third buffer. such action will depend upon the state of the fifo when the own bit has been updated in the first descriptor. in any case, lookahead will be performed to the third buffer and the information gathered will be stored in the chip, regardless of the state of the ownership bit. this activity continues until the pcnet pci ii controller recognizes the completion of the frame (the last byte of this receive message has been removed from the fifo). the pcnet pci ii controller will subsequently amd p r e l i m i n a r y 72 AM79C970A update the current rdte status with the end of frame (enp) indication set, write the message byte count (mcnt) for the entire frame into rmd2 and overwrite the current" entries in the csrs with the next" entries. media access control the media access control (mac) engine incorporates the essential protocol requirements for operation of a compliant ethernet/802.3 node, and provides the inter face between the fifo sub system and the manchester encoder/decoder (mendec). this section describes operation of the mac engine when operating in half duplex mode. when operating in half duplex mode, the mac engine is fully compliant to section 4 of iso/iec 8802 3 (ansi/ieee standard 1990 second edition) and ansi/ieee 802.3 (1985). when operating in full duplex mode, the mac engine behavior changes as described in the section full duplex operation". the mac engine provides programmable enhanced features designed to minimize host supervision, bus utilization, and pre or post message processing. these include the ability to disable retries after a colli sion, dynamic fcs generation on a frame by frame ba sis, automatic pad field insertion and deletion to enforce minimum frame size attributes, automatic re transmis sion without reloading the fifo, and automatic deletion of collision fragments. the two primary attributes of the mac engine are: n transmit and receive message data encapsulation framing (frame boundary delimitation, frame synchronization) addressing (source and destination address handling) error detection (physical medium transmission errors) n media access management medium allocation (collision avoidance) contention resolution (collision handling) transmit and receive message data encapsulation the mac engine provides minimum frame size enforce ment for transmit and receive frames. when apad_xmt (csr, bit 11) is set to one, transmit mes sages will be padded with sufficient bytes (containing 00h) to ensure that the receiving station will observe an information field (destination address, source address, length/type, data and fcs) of 64 bytes. when astrp_rcv (csr4, bit 10) is set to one, the receiver will automatically strip pad bytes from the received mes sage by observing the value in the length field, and strip ping excess bytes if this value is below the minimum data size (46 bytes). both features can be independently over ridden to allow illegally short (less than 64 bytes of frame data) messages to be transmitted and/or received. the use of this feature reduces bus utilization because the pad bytes are not transferred into or out of main memory. framing the mac engine will autonomously handle the con struction of the transmit frame. once the transmit fifo has been filled to the predetermined threshold (set by xmtsp in csr80), and access to the channel is cur rently permitted, the mac engine will commence the 7 byte preamble sequence (10101010b, where first bit transmitted is a 1). the mac engine will subsequently append the start frame delimiter (sfd) byte (10101011b) followed by the serialized data from the transmit fifo. once the data has been completed, the mac engine will append the fcs (most significant bit first) which was computed on the entire data portion of the frame. the data portion of the frame consists of des tination address, source address, length/type, and frame data. the user is responsible for the correct order ing and content in each of these fields in the frame. the receive section of the mac engine will detect an in coming preamble sequence and lock to the encoded clock. the internal mendec will decode the serial bit stream and present this to the mac engine. the mac will discard the first 8 bits of information before search ing for the sfd sequence. once the sfd is detected, all subsequent bits are treated as part of the frame. the mac engine will inspect the length field to ensure mini mum frame size, strip unnecessary pad characters (if enabled), and pass the remaining bytes through the re ceive fifo to the host. if pad stripping is performed, the mac engine will also strip the received fcs bytes, al though normal fcs computation and checking will oc cur. note that apart from pad stripping, the frame will be passed unmodified to the host. if the length field has a value of 46 or greater, all frame bytes including fcs will be passed unmodified to the receive buffer, regardless of the actual frame length. if the frame terminates or suffers a collision before 64 bytes of information (after sfd) have been received, the mac engine will automatically delete the frame from the receive fifo, without host intervention. the pcnet pci ii controller has the ability to accept runt packets for diagnostics purposes and proprietary networks. destination address handling the first 6 bytes of information after sfd will be inter preted as the destination address field. the mac engine provides facilities for physical (unicast), logical (multi cast) and broadcast address reception. p r e l i m i n a r y amd 73 AM79C970A error detection the mac engine provides several facilities which report and recover from errors on the medium. in addition, it protects the network from gross errors due to inability of the host to keep pace with the mac engine activity. on completion of transmission, the following transmit status is available in the appropriate transmit message descriptor (tmd) and control and status register (csr) areas: n the number of transmission retry attempts (one, more, rtry, and trc). n whether the mac engine had to defer (def) due to channel activity. n excessive deferral (exdef), indicating that the transmitter has experienced excessive deferral on this transmit frame, where excessive deferral is de fined in iso 8802 3 (ieee/ansi 802.3). n loss of carrier (lcar), indicating that there was an interruption in the ability of the mac engine to monitor its own transmission. repeated lcar er rors indicate a potentially faulty transceiver or net work connection. n late collision (lcol) indicates that the transmission suffered a collision after the slot time. this is indica tive of a badly configured network. late collisions should not occur in a normal operating network. n collision error (cerr) indicates that the transceiver did not respond with an sqe test message within the first 4 m s after a transmission was completed. this may be due to a failed transceiver, disconnected or faulty transceiver drop cable, or the fact the transceiver does not support this feature (or it is disabled). in addition to the reporting of network errors, the mac engine will also attempt to prevent the creation of any network error due to the inability of the host to service the mac engine. during transmission, if the host fails to keep the transmit fifo filled sufficiently, causing an un derflow, the mac engine will guarantee the message is either sent as a runt packet (which will be deleted by the receiving station) or has an invalid fcs (which will also cause the receiver to reject the message). the status of each receive message is available in the appropriate receive message descriptor (rmd) and csr areas. all received frames are passed to the host regardless of any error. the fram error will only be re ported if an fcs error is detected and there are a non integral number of bytes in the message. during the reception, the fcs is generated on every se rial bit (including the dribbling bits) coming from the ca ble, although the internally saved fcs value is only updated on the eighth bit (on each byte boundary). the mac engine will ignore up to 7 additional bits at the end of a message (dribbling bits), which can occur under normal network operating conditions. the framing error is reported to the user as follows: n if the number of dribbling bits are 1 to 7 and there is no fcs error, then there is no framing error (fram = 0). n if the number of dribbling bits are 1 to 7 and there is a fcs error, then there is also a framing error (fram = 1). n if the number of dribbling bits is zero, then there is no framing error. there may or may not be a fcs error. n if the number of dribbling bits is eight, then there is no framing error. fcs error will be reported and the receive message count will indicated one extra byte. counters are provided to report the receive collision count and runt packet count, for network statistics and utilization calculations. note that if the mac engine detects a received frame which has a 00b pattern in the preamble (after the first 8 bits which are ignored), the entire frame will be ig nored. the mac engine will wait for the network to go inactive before attempting to receive additional frames. media access management the basic requirement for all stations on the network is to provide fairness of channel allocation. the 802.3/ethernet protocols define a media access mecha nism which permits all stations to access the channel with equality. any node can attempt to contend for the channel by waiting for a predetermined time (inter pack et gap) after the last activity, before transmitting on the media. the channel is a multidrop communications me dia (with various topological configurations permitted) which allows a single station to transmit and all other stations to receive. if two nodes simultaneously contend for the channel, their signals will interact causing loss of data, defined as a collision. it is the responsibility of the mac to attempt to avoid and recover from a collision, to guarantee data integrity for the end to end transmission to the receiving station. medium allocation the ieee/ansi 802.3 standard (iso/iec 8802 3 1990) requires that the csma/cd mac monitor the medium for traffic by watching for carrier activity. when carrier is detected, the media is considered busy, and the mac should defer to the existing message. the iso 8802 3 (ieee/ansi 802.3) standard also al lows optional two part deferral after a receive message. see ansi/ieee std 802.3 1990 edition, 4.2.3.2.1: note: it is possible for the pls carrier sense indication to fail to be asserted during a collision on the media. if the deference process simply times the interframe gap based on this indication it is possible for a short amd p r e l i m i n a r y 74 AM79C970A interframe gap to be generated, leading to a potential reception failure of a subsequent frame. to enhance system robustness the following optional measures,as specified in 4.2.8, are recommended when interframe spacing part 1 is other than zero: 1. upon completing a transmission, start timing the interpacket gap, as soon as transmitting and carrier sense are both false. 2. when timing an interframe gap following reception, reset the interframe gap timing if carrier sense be comes true during the first 2/3 of the interframe gap timing interval. during the final 1/3 of the interval the timer shall not be reset to ensure fair access to the medium. an initial period shorter than 2/3 of the interval is permissible including zero." the mac engine implements the optional receive two part deferral algorithm, with a first part inter frame spacing time of 6.0 m s. the second part of the inter frame spacing interval is therefore 3.6 m s. the pcnet pci ii controller will perform the two part de ferral algorithm as specified in section 4.2.8 (process deference). the inter packet gap (ipg) timer will start timing the 9.6 m s interframespacing after the receive carrier is deasserted. during the first part deferral (inter frame spacing part1 - ifs1) the pcnet pci ii control ler will defer any pending transmit frame and respond to the receive message. the ipg counter will be cleared to zero continuously until the carrier deasserts, at which point the ipg counter will resume the 9.6 m s count once again. once the ifs1 period of 6.0 m s has elapsed, the pcnet pci ii controller will begin timing the second part deferral (inter frame spacing part2 - ifs2) of 3.6 m s. once ifs1 has completed, and ifs2 has commenced, the pcnet pci ii controller will not defer to a receive frame if a transmit frame is pending. this means that the pcnet pci ii controller will not attempt to receive the re ceive frame, since it will start to transmit, and generate a collision at 9.6 m s. the pcnet pci ii controller will com plete the preamble (64 bit) and jam (32 bit) sequence before ceasing transmission and invoking the random backoff algorithm. this transmit two part deferral algorithm is implemented as an option which can be disabled using the dxmt2pd bit in csr3. two part deferral after transmission is useful for ensuring that severe ipg shrinkage cannot occur in specific circumstances, causing a transmit message to follow a receive message so closely as to make them indistinguishable. during the time period immediately after a transmission has been completed, the external transceiver (in the case of a standard aui connected device), should generate the sqe test message (a nominal 10 mhz burst of 5-15 bit times duration) on the ci pair (within 0.6-1.6 m s after the transmission ceases). during the time period in which the sqe test message is expected the pcnet pci ii controller will not respond to receive carrier sense. see ansi/ieee std 802.3 1990 edition, 7.2.4.6 (1): at the conclusion of the output function, the dte opens a time window during which it expects to see the signal_quality_error signal asserted on the control in circuit. the time window begins when the carrier_status becomes carrier_off. if exe cution of the output function does not cause carrier_on to occur, no sqe test occurs in the dte. the duration of the window shall be at least 4.0 m s but no more than 8.0 m s. during the time window the carrier sense function is inhibited." the pcnet pci ii controller implements a carrier sense blinding" period of 4.0 m s length starting from the deassertion of carrier sense after transmission. this ef fectively means that when transmit two part deferral is enabled (dxmt2pd is cleared) the ifs1 time is from 4 m s to 6 m s after a transmission. however, since ipg shrinkage below 4 m s will rarely be encountered on a correctly configured network, and since the fragment size will be larger than the 4 m s blinding window, the ipg counter will be reset by a worst case ipg shrinkage/frag ment scenario and the pcnet pci ii controller will defer its transmission. if carrier is detected within the 4.0 to 6.0 m s ifs1 period, the pcnet pci ii controller will not restart the blinding" period, but only restart ifs1. collision handling collision detection is performed and reported to the mac engine by the integrated manchester encoder/decoder (mendec). if a collision is detected before the complete preamble/ sfd sequence has been transmitted, the mac engine will complete the preamble/sfd before appending the jam sequence. if a collision is detected after the pream ble/sfd has been completed, but prior to 512 bits being transmitted, the mac engine will abort the transmis sion, and append the jam sequence immediately. the jam sequence is a 32 bit all zeros pattern. the mac engine will attempt to transmit a frame a total of 16 times (initial attempt plus 15 retries) due to normal collisions (those within the slot time). detection of colli sion will cause the transmission to be re scheduled to a time determined by the random backoff algorithm. if a single retry was required, the one bit will be set in the transmit frame status. if more than one retry was re quired, the more bit will be set. if all 16 attempts experi enced collisions, the rtry bit will be set (one and more will be clear), and the transmit message will be flushed from the fifo. if retries have been disabled by setting the drty bit in csr15, the mac engine will abandon transmission of the frame on detection of the first collision. in this case, only the rtry bit will be set and the transmit message will be flushed from the fifo. p r e l i m i n a r y amd 75 AM79C970A if a collision is detected after 512 bit times have been transmitted, the collision is termed a late collision. the mac engine will abort the transmission, append the jam sequence and set the lcol bit. no retry attempt will be scheduled on detection of a late collision, and the trans mit message will be flushed from the fifo. the iso 8802 3 (ieee/ansi 802.3) standard requires use of a truncated binary exponential backoff" algorithm which provides a controlled pseudo random mechanism to enforce the collision backoff interval, be fore re transmission is attempted. see ansi/ieee std 802.3 1990 edition, 4.2.3.2.5: at the end of enforcing a collision (jamming), the csma/cd sublayer delays before attempting to re transmit the frame. the delay is an integer multiple of slot time. the number of slot times to delay before the nth re transmission attempt is chosen as a uniformly distributed random integer r in the range: 0 r <2k where k = min (n,10)." the pcnet pci ii controller provides an alternative algo rithm, which suspends the counting of the slot time/ipg during the time that receive carrier sense is detected. this aids in networks where large numbers of nodes are present, and numerous nodes can be in collision. it ef fectively accelerates the increase in the backoff time in busy networks, and allows nodes not involved in the col lision to access the channel whilst the colliding nodes await a reduction in channel activity. once channel ac tivity is reduced, the nodes resolving the collision time out their slot time counters as normal. this modified backoff algorithm is enabled when emba (csr3, bit 3) is set to one. transmit operation the transmit operation and features of the pcnet pci ii controller are controlled by programmable options. the pcnet pci ii controller offers a 272 byte transmit fifo to provide frame buffering for increased system latency, automatic re transmission with no fifo reload, and automatic transmit padding. transmit function programming automatic transmit features such as retry on collision, fcs generation/transmission, and pad field insertion can all be programmed to provide flexibility in the (re )transmission of messages. disable retry on collision (drty) is controlled by the drty bit of the mode register (csr15) in the initialization block. automatic pad field insertion is controlled by the apad_xmt bit in csr4. the disable fcs generation/transmission feature can be programmed as a static feature or dynamically on a frame by frame basis. transmit fifo watermark (xmtfw) in csr80 sets the point at which the bmu requests more data from the transmit buffers for the fifo. a minimum of xmtfw empty spaces must be available in the transmit fifo be fore the bmu will request the system bus in order to transfer transmit frame data into the transmit fifo. transmit start point (xmtsp) in csr80 sets the point when the transmitter actually attempts to transmit a frame onto the media. a minimum of xmtsp bytes must be written to the transmit fifo for the current frame be fore transmission of the current frame will begin. (when automatically padded packets are being sent, it is con ceivable that the xmtsp is not reached when all of the data has been transferred to the fifo. in this case, the transmission will begin when all of the frame data has been placed into the transmit fifo.) the default value of xmtsp is 01b, meaning there has to be 64 bytes in the transmit fifo to start a transmission. automatic pad generation transmit frames can be automatically padded to extend them to 64 data bytes (excluding preamble). this allows the minimum frame size of 64 bytes (512 bits) for 802.3/ethernet to be guaranteed with no software inter vention from the host/controlling process. setting the apad_xmt bit in csr4 enables the automatic padding feature. the pad is placed between the llc data field and fcs field in the 802.3 frame. fcs is always added if the frame is padded, regardless of the state of dxmtfcs (csr15, bit 3) or add_fcs/no_fcs (tmd1, bit 29). the transmit frame will be padded by bytes with the value of 00h. the default value of apad_xmt is 0, which will disable automatic pad gen eration after h_reset. it is the responsibility of upper layer software to correctly define the actual length field contained in the message to correspond to the total number of llc data bytes en capsulated in the frame (length field as defined in the iso 8802 3 (ieee/ansi 802.3) standard). the length value contained in the message is not used by the pcnet pci ii controller to compute the actual number of pad bytes to be inserted. the pcnet pci ii controller will append pad bytes dependent on the actual number of bits transmitted onto the network. once the last data byte of the frame has completed, prior to appending the fcs, the pcnet pci ii controller will check to ensure that 544 bits have been transmitted. if not, pad bytes are added to extend the frame size to this value, and the fcs is then added. amd p r e l i m i n a r y 76 AM79C970A preamble 1010....1010 sfd 10101011 destination address source address length llc data pad fcs 4 bytes 46 ?1500 bytes 2 bytes 6 bytes 6 bytes 8 bits 56 bits 19436a 37 figure 34. iso 8802 3 (ieee/ansi 802.3) data frame the 544 bit count is derived from the following : minimum frame size (excluding 64 bytes 512 bits preamble/sfd, including fcs) preamble/sfd size 8 bytes 64 bits fcs size 4 bytes 32 bits at the point that fcs is to be appended, the transmit ted frame should contain: preamble/sfd + (min frame size - fcs) 64 + (512 - 32) = 544 bits a minimum length transmit frame from the pcnet pci ii controller will therefore be 576 bits, after the fcs is appended. transmit fcs generation automatic generation and transmission of fcs for a transmit frame depends on the value of dxmtfcs (csr15, bit 3). if dxmtfcs is cleared to zero, the transmitter will generate and append the fcs to the transmitted frame. if the automatic padding feature is in voked (apad_xmt is set in csr4), the fcs will be ap pended by the pcnet pci ii controller regardless of the state of dxmtfcs or add_fcs/no_fcs (tmd1, bit 29). note that the calculated fcs is transmitted most significant bit first. the default value of dxmtfcs is 0 after h_reset. add_fcs (tmd1, bit 29) allows the automatic genera tion and transmission of fcs on a frame by frame basis. dxmtfcs should be cleared to zero in this mode. to generate fcs for a frame, add_fcs must be set in the first descriptor of a frame (stp is set to one). note that bit 29 of tmd1 has the function of add_fcs if swstyle (bcr20, bits 7-0) is programmed to zero, two or three. when swstyle is set to one for ilacc backwards compatibility, bit 29 of tmd1 changes its function to no_fcs. when dxmtfcs is cleared to zero and no_fcs is set to one in the last descriptor of a frame (enp is set to one), the pcnet pci ii controller will not generate and append an fcs to a transmit frame. transmit exception conditions exception conditions for frame transmission fall into two distinct categories. those which are the result of normal network operation, and those which occur due to abnor mal network and/or host related events. normal events which may occur and which are handled autonomously by the pcnet pci ii controller include col lisions within the slot time with automatic retry. the pcnet pci ii controller will ensure that collisions which occur within 512 bit times from the start of transmission (including preamble) will be automatically retried with no host intervention. the transmit fifo ensures this by guaranteeing that data contained within the fifo will not be overwritten until at least 64 bytes (512 bits) of pre amble plus address, length and data fields have been transmitted onto the network without encountering a col lision. note that if drty (csr15, bit 5) is set to one or if the network interface is operating in full duplex mode, no collision handling is required, and any byte of frame data in the fifo can be overwritten as soon as it is transmitted. if 16 total attempts (initial attempt plus 15 retries) fail, the pcnet pci ii controller sets the rtry bit in the current transmit tdte in host memory (tmd2), gives up ownership (resets the own bit to zero) for this frame, and processes the next frame in the transmit ring for transmission. abnormal network conditions include: n loss of carrier. n late collision. n sqe test error. (does not apply to 10base t port.) these conditions should not occur on a correctly config ured 802.3 network operating in half duplex mode, and will be reported if they do. none of these conditions will occur on a network operating in full duplex mode. (see the section full duplex operation" for more detail.) when an error occurs in the middle of a multi buffer frame transmission, the error status will be written in the p r e l i m i n a r y amd 77 AM79C970A current descriptor. the own bit(s) in the subsequent descriptor(s) will be cleared until the stp (the next frame) is found. loss of carrier when operating in half duplex mode, a loss of carrier condition will be reported if the pcnet pci ii controller cannot observe receive activity whilst it is transmitting on the aui or gpsi port. in aui mode, after the pcnet pci ii controller initiates a transmission it will ex pect to see data looped back" on the di pair. this will internally generate a carrier sense", indicating that the integrity of the data path to and from the mau is intact, and that the mau is operating correctly. this carrier sense" signal must be asserted before the last bit is transmitted on do . if carrier sense" does not become active in response to the data transmission, or becomes inactive before the end of transmission, the loss of car rier (lcar) error bit will be set in tmd2 after the frame has been transmitted. the frame will not be retried on the basis of an lcar error. in gpsi mode, lcar will be asserted if rxen does not go active during the transmission. when the 10base t port is selected, lcar will be re ported for every frame transmitted while the network in terface is in the link fail state. late collision a late collision will be reported if a collision condition oc curs after one slot time (512 bit times) after the transmit process was initiated (first bit of preamble commenced). the pcnet pci ii controller will abandon the transmit process for that frame, set late collision (lcol) in the associated tmd2, and process the next transmit frame in the ring. frames experiencing a late collision will not be retried. recovery from this condition must be per formed by upper layer software. sqe test error during the inter packet gap time following the comple tion of a transmitted message, the aui ci pair is as serted by some transceivers as a self test. the integral manchester encoder/decoder will expect the sqe test message (nominal 10 mhz sequence) to be returned via the ci pair within a 40 network bit time period after di goes inactive (this does not apply if the 10base t port is selected). if the ci input is not asserted within the 40 network bit time period following the completion of transmission, then the pcnet pci ii controller will set the cerr bit in csr0. in gpsi mode, clsn must be asserted after the transmission or otherwise cerr will be set. cerr will be asserted in 10base t mode after transmit if t mau is in link fail state. cerr will never cause inta to be activated. it will, however, set the err bit csr0. receive operation the receive operation and features of the pcnet-pci ii controller are controlled by programmable options. the pcnet-pci ii controller offers a 256-byte receive fifo to provide frame buffering for increased system latency, automatic flushing of collision fragments (runt packets), automatic receive pad stripping and a variety of address match options. receive function programming automatic pad field stripping is enabled by setting the astrp_rcv bit in csr4. this can provide flexibility in the reception of messages using the 802.3 frame format. all receive frames can be accepted by setting the prom bit in csr15. acceptance of unicast and broadcast frames can be individually turned off by setting the drcvpa or drcvbc bits in csr15. the physical ad- dress register (csr12 to csr14) stores the address the pcnet-pci ii controller compares to the destination address of the incoming frame for a unicast address match. the logical address filter register (csr8 to csr11) serves as a hash filter for multicast address match. the point at which the bmu will start to transfer data from the receive fifo to buffer memory is controlled by the rcvfw bits in csr80. the default established dur- ing h_reset is 01b which sets the watermark flag at 64 bytes filled. for test purposes, the pcnet-pci ii controller can be programmed to accept runt packets by setting rpa in csr124. address matching the pcnet-pci ii controller supports three types of ad- dress matching: unicast, multicast, and broadcast. the normal address matching procedure can be modified by programming three bits in csr15, the mode register (prom, drcvpa, and drcvbc). if the first bit received after the start of frame delimiter (the least significant bit of the first byte of the destination address field) is 0, the frame is unicast, which indicates that the frame is meant to be received by a single node. if the first bit received is 1, the frame is multicast, which indicates that the frame is meant to be received by a group of nodes. if the destination address field contains all ones, the frame is broadcast, which is a special type of multicast. frames with the broadcast address in the destination address field are meant to be received by all nodes on the local area network. amd p r e l i m i n a r y 78 AM79C970A when a unicast frame arrives at the pcnet pci ii con troller, the controller will accept the frame if the destina tion address field of the incoming frame exactly matches the 6 byte station address stored in the physical ad dress registers (padr, csr12 to csr14). the byte or dering is such that the first byte received from the network (after the sfd) must match the least significant byte of csr12 (padr[7:0]), and the sixth byte received must match the most significant byte of csr14 (padr[47:40]). when drcvpa (csr15, bit 13) is set to one, the pcnet pci ii controller will not accept unicast frames. if the incoming frame is multicast, the pcnet pci ii con troller performs a calculation on the contents of the destination address field to determine whether or not to accept the frame. this calculation is explained in the section that describes the logical address filter (ladrf). when all bits of the ladrf registers are 0, no multicast frames are accepted, except for broadcast frames. although broadcast frames are classified as special multicast frames, they are treated differently by the pcnet pci ii controller hardware. broadcast frames are always accepted, except when drcvbc (csr15, bit 14) is set. none of the address filtering described above applies when the pcnet pci ii controller is operating in the pro miscuous mode. in the promiscuous mode, all properly formed packets are received, regardless of the contents of their destination address fields. the promiscuous mode overrides the disable receive broadcast bit (drcvbc bit l4 in the mode register) and the disable receive physical address bit (drcvpa, csr15, bit 13). the pcnet pci ii controller operates in promiscuous mode when prom (csr15, bit 15) is set. in addition, the pcnet pci ii controller provides the ex ternal address detection interface (eadi) to allow external address filtering. see the section external ad dress detection interface" for further detail. the receive descriptor entry rmd1 contains three bits that indicate which method of address matching caused the pcnet pci ii controller to accept the frame. note that these indicator bits are only available when the pcnet pci ii controller is programmed to use 32 bit structures for the descriptor entries (bcr20, bit 7-0, swstyle is set to one, two or three). pam (rmd1, bit 22) is set by the pcnet pci ii controller when it accepted the received frame due to a match of the frame's destination address with the content of the physical address register. lafm (rmd1, bit 21) is set by the pcnet pci ii control ler when it accepted the received frame based on the value in the logical address filter register. bam (rmd1, bit 20) is set by the pcnet pci ii controller when it accepted the received frame because the frame's destination address is of the type broadcast". if drcvbc (csr15, bit 14) is cleared to zero, only bam, but not lafm will be set when a broadcast frame is received, even if the logical address filter is pro grammed in such a way that a broadcast frame would pass the hash filter. if drcvbc is set to one and the logical address filter is programmed in such a way that a broadcast frame would pass the hash filter, lafm will be set on the reception of a broadcast frame. when the pcnet pci ii controller operates in promiscu ous mode and none of the three match bits is set, it is an indication that the pcnet pci ii controller only accepted the frame because it was in promiscuous mode. when the pcnet pci ii controller is not programmed to be in promiscuous mode, but the eadi interface is en abled, then when none of the three match bits is set, it is an indication that the pcnet pci ii controller only ac cepted the frame because it was not rejected by driving the ear pin low within 64 bytes after sfd. table 6. receive address match pam lafm bam drcvbc comment 0 0 0 x frame accepted due to prom = 1 or no eadi reject 1 0 0 x physical address match 0 1 0 0 logical address filter match; frame is not of type broadcast 0 1 0 1 logical address filter match; frame can be of type broadcast 0 0 1 0 broadcast frame automatic pad stripping during reception of an 802.3 frame the pad field can be stripped automatically. setting astrp_rcv (csr4, bit 0) to one enables the automatic pad stripping feature. the pad field will be stripped before the frame is passed to the fifo, thus preserving fifo space for additional frames. the fcs field will also be stripped, since it is computed at the transmitting station based on the data and pad field characters, and will be invalid for a receive frame that has had the pad characters stripped. p r e l i m i n a r y amd 79 AM79C970A the number of bytes to be stripped is calculated from the embedded length field (as defined in the iso 8802 3 (ieee/ansi 802.3) definition) contained in the frame. the length indicates the actual number of llc data bytes contained in the message. any received frame which contains a length field less than 46 bytes will have the pad field stripped (if astrp_rcv is set). receive frames which have a length field of 46 bytes or greater will be passed to the host unmodified. the figure below shows the byte/bit ordering of the re ceived length field for an 802.3 compatible frame format. preamble 1010....1010 sfd 10101011 destination address source address length llc data pad fcs 4 bytes 46 ?1500 bytes 2 bytes 6 bytes 6 bytes 8 bits 56 bits start of frame at time = 0 increasing time bit 0 bit 7 bit 0 bit 7 most significant byte least significant byte 1 ?1500 bytes 45 ?0 bytes 19436a 38 figure 35. 802.3 frame and length field transmission order since any valid ethernet type field value will always be greater than a normal 802.3 length field ( 3 46), the pcnet pci ii controller will not attempt to strip valid ethernet frames. note that for some network protocols, the value passed in the ethernet type and/or 802.3 length field is not compliant with either standard and may cause problems if pad stripping is enabled. receive fcs checking reception and checking of the received fcs is per formed automatically by the pcnet pci ii controller. note that if the automatic pad stripping feature is en abled, the fcs for padded frames will be verified against the value computed for the incoming bit stream including pad characters, but the fcs value for a pad ded frame will not be passed to the host. if an fcs error is detected in any frame, the error will be reported in the crc bit in rmd1. receive exception conditions exception conditions for frame reception fall into two distinct categories: those which are the result of normal network operation, and those which occur due to abnor mal network and/or host related events. normal events which may occur and which are handled autonomously by the pcnet pci ii controller are basi cally collisions within the slot time and automatic runt packet rejection. the pcnet pci ii controller will ensure that collisions which occur within 512 bit times from the start of reception (excluding preamble) will be automati cally deleted from the receive fifo with no host inter vention. the receive fifo will delete any frame which is composed of fewer than 64 bytes provided that the runt packet accept (rpa bit in csr124) feature has not been enabled and the network interface is operating in half duplex mode. this criterion will be met regardless of whether the receive frame was the first (or only) frame in the fifo or if the receive frame was queued behind a previously received message. amd p r e l i m i n a r y 80 AM79C970A abnormal network conditions include: n fcs errors n late collision host related receive exception conditions include miss, buff, and oflo. these are described in the section buffer management unit". loopback operation loopback is a mode of operation intended for system di agnostics. in this mode, the transmitter and receiver are both operating at the same time so that the controller re ceives its own transmissions. the controller provides two basic types of loopback. in internal loopback mode, the transmitted data is looped back to the receiver inside the controller without actually transmitting any data to the external network. the receiver will move the re ceived data to the next receive buffer, where it can be examined by software. alternatively, in external loop back mode, data can be transmitted to and received from the external network. loopback operation is enabled by setting loop (csr15, bit 2) to one. the mode of loopback operation is dependent on the active network port and on the set tings of the control bits intl (csr15, bit 6), mendecl (csr15, bit 10) and tmauloop (bcr2, bit 14). the setting of the full duplex control bits in bcr9 has no ef fect on the loopback operation. gpsi loopback modes when gpsi is the active network port there are only two modes of loopback operation: internal and external loopback. the settings of mendecl and tmauloop have no effect for this port. when intl is set to one, internal loopback is selected. data coming out of the transmit fifo is fed directly to the receive fifo. all gpsi outputs are inactive, inputs are ignored. external loopback operation is selected by setting intl to zero. data is transmitted to the network and is ex pected to be looped back to the gpsi receive pins out side the chip. collision detection is active in this mode. aui loopback modes when aui is the active network port there are three modes of loopback operation: internal with and without mendec and external loopback. the setting of tmauloop has no effect for this port. when intl and mendecl are set to one, internal loopback without mendec is selected. data coming out of the transmit fifo is fed directly to the receive fifo. the aui transmitter is disabled and signals on the receive and collision inputs are ignored. when intl is set to one and mendecl is cleared to zero, internal loopback including the mendec is se lected. data is routed from the transmit fifo through the mendec back to the receive fifo. no data is trans mitted to the network. all signals on the receive and colli sion inputs are ignored. external loopback operation is selected by setting intl to zero. the programming of mendecl has no effect in this mode. the aui transmitter is enabled and data is transmitted to the network. the pcnet pci ii controller expects data to be looped back to the receive inputs out side the chip. collision detection is active in this mode. t mau loopback modes when t mau is the active network port there are four modes of loopback operation: internal loopback with and without mendec and two external loopback modes. when intl and mendecl are set to one, internal loopback without mendec is selected. data coming out of the transmit fifo is fed directly to the receive fifo. the t mau does not transmit any data to the net work, but it continues to send link pulses. all signals on the receive inputs are ignored. lcar (tmd2, bit 27) will always read zero, regardless of the link state. the pro gramming of tmauloop has no effect. when intl is set to one and mendecl is cleared to zero, internal loopback including the mendec is se lected. data is routed from the transmit fifo through the mendec back to the receive fifo. the t mau does not transmit any data to the network, but it contin ues to send link pulses. all signals on the receive inputs are ignored. lcar (tmd2, bit 27) will always read zero, regardless of the link state. the programming of tmauloop has no effect. external loopback operation works slightly different when the t mau is the active network port. in a 10base t network, the hub does not generate a re ceive carrier back to the pcnet pci ii controller while the chip is transmitting. the t mau provides this func tion internally. a true external loopback covering all the components on the printed circuit board can only be per formed by using a special connector that connects the transmit pins of the rj 45 jack to its receive pins. when intl is cleared to zero and tmauloop is set to one, data is transmitted to the network and is expected to be routed back to the chip. collision detection is disabled in this mode. the link state machine is forced into the link pass state. lcar will always read zero. the program ming of mendecl has no effect in this mode. the pcnet pci ii controller provides a special external loopback mode that allows the device to be connected to a live 10base t network. the virtual external loop back mode is invoked by setting intl and tmauloop to zero. in this mode, data coming out of the transmit fifo is fed directly into the receive fifo. additionally, all transmit data is output to the network. the link state p r e l i m i n a r y amd 81 AM79C970A machine is active as is the collision detection logic. the programming of mendecl has no effect in this mode. miscellaneous loopback features all transmit and receive function programming, such as automatic transmit padding and receive pad stripping, operates identically in loopback as in normal operation. loopback mode can be performed with any frame size. runt packet accept is internally enabled (rpa bit in csr124 is not affected) when any loopback mode is in voked. this is to be backwards compatible to the c lance (am79c90) software. since the pcnet pci ii controller has two fcs genera tors there are no more restrictions on fcs generation or checking or on testing multicast address detection as they exist in the half duplex pcnet family devices and in the c lance and ilacc. on receive the pcnet pci ii controller now provides true fcs status. the descriptor for a frame with an fcs error will have the fcs bit (rmd1, bit 27) set to one. the fcs generator on the transmit side can still be disabled by setting dxmtfcs (csr15, bit 3) to one. in internal loopback operation the pcnet pci ii control ler provides a special mode to test the collision logic. when fcoll (csr15, bit 4) is set to one, a collision is forced during every transmission attempt. this will re sult in a retry error. magic packet mode magic packet mode is enabled by performing three steps. first, the pcnet pci ii controller must be put into suspend mode (see description of csr5, bit 0), allowing any current network activity to finish. next, mpmode (csr5, bit 1) must be set to one if it has not been set already. finally, either sleep must be asserted (hard- ware control) or mpen (csr5, bit 2) must be set to one (software control). in magic packet mode, the pcnet-pci ii controller re- mains fully powered-up (all v dd and v ddb pins must re main at their supply levels). the device will not generate any bus master transfers. no transmit operations will be initiated on the network. the device will continue to re ceive frames from the network, but all frames will be automatically flushed from the receive fifo. slave ac cesses to the pcnet pci ii controller are still possible. magic packet mode can be disabled at any time by deasserting sleep or clearing mpen. a magic packet frame is a frame that is addressed to the pcnet-pci ii controller and contains a data sequence in its data field made up of sixteen consecutive physical addresses (padr[47:0]). the pcnet-pci ii controller will search incoming frames until it finds a magic packet frame. the device starts scanning for the sequence af- ter processing the length field of the frame. the data se- quence can begin anywhere in the data field of the frame, but must be detected before the pcnet-pci ii controller reaches the frame's fcs field. the pcnet- pci ii controller is designed such that it does not need the synchronization sequence (6 bytes of all ones (ffffffffffffh) at the beginning of the data field), to correctly recognize the proper data sequence. how- ever, any deviation of the incoming frame's magic pack- et data sequence from the required physical address sequence, even by a single bit, will prevent the detection of that frame as a magic packet frame. the pcnet-pci ii controller supports two different modes of address detection for a magic packet frame. if mpplba (csr5, bit 5) is at its default value of zero, the pcnet-pci ii controller will only detect a magic packet frame if the destination address of the frame matches the content of the physical address register (padr). if mpplba is set to one, the destination ad- dress of the magic packet frame can be unicast, multi- cast, or broadcast. note that the setting of mpplba only effects the address detection of the magic packet frame. the magic packet data sequence must be made up of sixteen consecutive physical addresses (padr[47:0]), even if the packet contains a valid desti- nation address that is not the physical address. when the pcnet-pci ii controller detects a magic pack- et frame, it sets mpint (csr5, bit 4) to one. if inea (csr0, bit 6) and mpinte (csr5, bit 3) are set to one, inta will be asserted. the interrupt signal can be used wake up the system. as an alternative, one of the four led pins can be programmed to indicated that a magic packet frame has been received. mpse (bcr4C7, bit 9) must be set to one to enable that function. note that the polarity of the led pin can be programmed to be active high by setting ledpol (bcr4C7, bit 14) to one. once a magic packet frame is detected, the pcnet-pci ii controller will discard the frame internally, but will not resume normal transmit and receive operations until sleep is deasserted or mpen is cleared, disabling magic packet mode. once either of these events has occurred indicating that the system has detected the as- sertion of inta or an led pin and is now awake, the controller will continue polling the receive and transmit descriptor rings where it left off. reinitialization should not be performed. if magic packet mode is disabled by the deassertion of sleep , then in order to immediately reenable magic packet mode, the sleep pin must remain deasserted for at least 200 ns before it is reasserted. if magic packet mode is disabled by clearing mpen, then it may be im- mediately reenabled by setting mpen back to one. the bus interface clock (clk) must continue running if inta is used to indicate the detection of a magic packet. amd p r e l i m i n a r y 82 AM79C970A a system that wants to stop the clock during magic packet mode should use one of the led pins as an indi cator of magic packet frame detection. it should also stop the clock after enabling magic packet mode, other wise pci bus activity, including accessing csr5 to set mpmode and possibly mpen to a one, could be af fected. the clock should be restarted before magic packet mode is disabled if mpen is being cleared or the clock must be restarted right after magic packet mode is disabled if sleep is being deasserted. otherwise, the receive fifo may overflow if new frames arrive. the network clock (xtal1) must continue running at all times while in magic packet mode. manchester encoder/decoder the integrated manchester encoder/decoder (mendec) provides the pls (physical layer signaling) functions required for a fully compliant iso 8802-3 (ieee/ansi 802.3) station. the mendec provides the encoding function for data to be transmitted on the net- work using the high accuracy on-board oscillator, driven by either the crystal oscillator or an external cmos level compatible clock. the mendec also provides the de- coding function from data received from the network. the mendec contains a power on reset (por) cir- cuit, which ensures that all analog portions of the pcnet-pci ii controller are forced into their correct state during power up, and prevents erroneous data trans- mission and/or reception during this time. external crystal characteristics when using a crystal to drive the oscillator, the following crystal specification may be used to ensure less than 0.5 ns jitter at do : table 7. crystal characteristics parameter min nom max units 1. parallel resonant frequency 20 mhz 2. resonant frequency error -50 +50 ppm 3. change in resonant frequency with respect to temperature (0 - 70 c)* -40 +40 ppm 4. crystal load capacitance 20 50 pf 5. motional crystal capacitance (c1) 0.022 pf 6. series resistance 35 ohm 7. shunt capacitance 7pf 8. drive level tbd mw * requires trimming specification, not trim is 50 ppm total. external clock drive characteristics when driving the oscillator from a cmos level external clock source, xtal2 must be left floating (unconnected). an external clock having the following characteristics must be used to ensure less than 0.5 ns jitter at do . table 8. external clock source characteristics clock frequency: 20 mhz 0.01% rise/fall time (tr/tf): <= 6 ns from 0.5 v to vdd -0.5 v xtal1 high/low time (thigh/tlow): 20 ns min. xtal1 falling edge to falling edge jitter: < 0.2 ns at 2.5 v input (vdd/2) mendec transmit path the transmit section encodes separate clock and nrz data input signals into a standard manchester encoded serial bit stream. the transmit outputs (do ) are de signed to operate into terminated transmission lines. when operating into a 78 w terminated transmission line, the transmit signaling meets the required output p r e l i m i n a r y amd 83 AM79C970A levels and skew for cheapernet, ethernet and ieee 802.3. transmitter timing and operation a 20 mhz fundamental mode crystal oscillator provides the basic timing reference for the mendec portion of the pcnet pci ii controller. the crystal frequency is divided by two to create the internal transmit clock refer ence. both the 10 mhz and 20 mhz clocks are fed into the manchester encoder. the internal transmit clock is used by the mendec to synchronize the internal trans mit data (itxdat) and internal transmit enable (itxen) from the controller. the internal transmit clock is also used as a stable bit rate clock by the receive sec tion of the mendec and controller. the oscillator requires an external 0.01% timing refer ence. if an external crystal is used, the accuracy require ments are tighter because allowance for the on board parasitics must be made to deliver a final accuracy of 0.01%. transmission is enabled by the controller. as long as the itxen request remains active, the serial output of the controller will be manchester encoded and appear at do . when the internal request is dropped by the con troller, the differential transmit outputs go to one of two idle states, dependent on tsel in the mode register (csr15, bit 9): table 9. tsel effect tsel low: the idle state of do yields zero differential to operate transformer coupled loads. tsel high: in this idle state, do+ is positive with respect to do- (logical high). receiver path the principal functions of the receiver are to signal the pcnet pci ii controller that there is information on the receive pair, and separate the incoming manchester en coded data stream into clock and nrz data. the receiver section (see the figure below) consists of two parallel paths. the receive data path is a zero threshold, wide bandwidth line receiver. the carrier path is an offset threshold bandpass detecting line receiver. both receivers share common bias networks to allow operation over a wide input common mode range. noise reject filter data receiver carrier detect circuit manchester decoder irxdat* irxclk* irxen* di *internal signal 19436a 39 figure 36. receiver block diagram input signal conditioning transient noise pulses at the input data stream are re jected by the noise rejection filter. pulse width rejec tion is proportional to transmit data rate. the carrier detection circuitry detects the presence of an incoming data frame by discerning and rejecting noise from expected manchester data, and controls the stop and start of the phase lock loop during clock acqui sition. clock acquisition requires a valid manchester bit pattern of 1010b to lock onto the incoming message. when input amplitude and pulse width conditions are met at di , the internal enable signal from the mendec to controller (irxen) is asserted and a clock acquisition cycle is initiated. clock acquisition when there is no activity at di (receiver is idle), the re ceive oscillator is phase locked to the internal transmit clock. the first negative clock transition (bit cell center of first valid manchester zero) after irxen is asserted amd p r e l i m i n a r y 84 AM79C970A interrupts the receive oscillator. the oscillator is then re started at the second manchester zero (bit time 4) and is phase locked to it. as a result, the mendec acquires the clock from the incoming manchester bit pattern in 4 bit times with a 1010b manchester bit pattern. irxclk and irxdat are enabled 1/4 bit time after clock acquisition in bit cell 5. irxdat is at a high state when the receiver is idle (no irxclk). irxdat however, is undefined when clock is acquired and may remain high or change to low state whenever irxclk is enabled. at 1/4 bit time into bit cell 5, the controller portion of the pcnet pci ii controller sees the first irxclk transition. this also strobes in the incoming fifth bit to the mendec as manchester one. irxdat may make a transition af ter the irxclk rising edge in bit cell 5, but its state is still undefined. the manchester one at bit 5 is clocked to irxdat output at 1/4 bit time in bit cell 6. pll tracking after clock acquisition, the phase locked clock is com pared to the incoming transition at the bit cell center (bcc) and the resulting phase error is applied to a cor rection circuit. this circuit ensures that the phase locked clock remains locked on the received signal. individual bit cell phase corrections of the voltage con trolled oscillator (vco) are limited to 10% of the phase difference between bcc and phase locked clock. hence, input data jitter is reduced in irxclk by 10 to 1. carrier tracking and end of message the carrier detection circuit monitors the di inputs after irxen is asserted for an end of message. irxen deas serts 1 to 2 bit times after the last positive transition on the incoming message. this initiates the end of recep tion cycle. the time delay from the last rising edge of the message to irxen deassert allows the last bit to be strobed by irxclk and transferred to the controller sec tion, but prevents any extra bit(s) at the end of message. data decoding the data receiver is a comparator with clocked output to minimize noise sensitivity to the di inputs. input error is less than 35 mv to minimize sensitivity to input rise and fall time. irxclk strobes the data receiver output at 1/4 bit time to determine the value of the manchester bit, and clocks the data out on irxdat on the following irxclk. the data receiver also generates the signal used for phase detector comparison to the internal mendec voltage controlled oscillator (vco). jitter tolerance definition the mendec utilizes a clock capture circuit to align its internal data strobe with an incoming bit stream. the clock acquisition circuitry requires four valid bits with the values 1010b. the clock is phase locked to the negative transition at the bit cell center of the second zero in the pattern. since data is strobed at 1/4 bit time, manchester transi tions which shift from their nominal placement through 1/4 bit time will result in improperly decoded data. with this as the criterion for an error, a definition of jitter handling is: the peak deviation approaching or crossing 1/4 bit cell position from nominal input transition, for which the mendec section will properly decode data. attachment unit interface the attachment unit interface (aui) is the pls (physi cal layer signaling) to pma (physical medium attach ment) interface which effectively connects the dte to a mau. the differential interface provided by the pcnet pci ii controller is fully compliant to section 7 of iso 8802 3 (ansi/ieee 802.3). after the pcnet pci ii controller initiates a transmission it will expect to see data looped back" on the di pair (when the aui port is selected). this will internally gen erate a carrier sense", indicating that the integrity of the data path to and from the mau is intact, and that the mau is operating correctly. this carrier sense" signal must be asserted before end of transmission. if "carrier sense" does not become active in response to the data transmission, or becomes inactive before the end of transmission, the loss of carrier (lcar) error bit will be set in the transmit descriptor ring (tmd2, bit 27) after the frame has been transmitted. differential input termination the differential input for the manchester data (di ) is externally terminated by two 40.2 w resistors and one optional common mode bypass capacitor, as shown in the diagram below. the differential input impedance, z idf , and the common mode input impedance, z icm , are specified so that the ethernet specification for cable termination impedance is met using standard 1% resis tor terminators. if sip devices are used, 39 ohms is also a suitable value. the ci differential inputs are termi nated in exactly the same way as the di pair. p r e l i m i n a r y amd 85 AM79C970A pcnet-pci ii di+ di- 40.2 w 40.2 w 0.01 m f to 0.1 m f aui isolation transformer 19436a 40 figure 37. aui differential input termination collision detection a mau detects the collision condition on the network and generates a 10 mhz differential signal at the ci inputs. this collision signal passes through an input stage which detects signal levels and pulse duration. when the signal is detected by the mendec it sets the iclsn line high. the condition continues for approxi mately 1.5 bit times after the last low to high transi tion on ci . twisted pair transceiver this section describes operation of the twisted pair transceiver (t mau) when operating in half duplex mode. when in half duplex mode, the t mau implements the medium attachment unit (mau) func tions for the twisted pair medium as specified by the supplement to ieee 802.3 standard (type 10base t). when operating in full duplex mode, the mac engine behavior changes as described in the section full duplex operation". the t mau provides twisted pair driver and receiver cir cuits, including on board transmit digital predistortion and receiver squelch and a number of additional fea tures including link status indication, automatic twisted pair receive polarity detection/correction and indication, receive carrier sense, transmit active and collision present indication. twisted pair transmit function the differential driver circuitry in the txd and txp pins provides the necessary electrical driving capability and the pre distortion control for transmitting signals over maximum length twisted pair cable, as specified by the 10base t supplement to the iso 8802 3 (ieee/ansi 802.3) standard. the transmit function for data output meets the propagation delays and jitter specified by the standard. twisted pair receive function the receiver complies with the receiver specifications of the iso 8802 3 (ieee/ansi 802.3) 10base t stan dard, including noise immunity and received signal re jection criteria (smart squelch"). signals meeting these criteria appearing at the rxd differential input pair are routed to the mendec. the receiver function meets the propagation delays and jitter requirements specified by the standard. the receiver squelch level drops to half its threshold value after unsquelch to allow reception of minimum amplitude signals and to offset carrier fade in the event of worst case signal attenuation and crosstalk noise conditions. note that the 10base t standard defines the receive input amplitude at the external media dependent inter face (mdi). filter and transformer loss are not specified. the t mau receiver squelch levels are defined to account for a 1 db insertion loss at 10 mhz, which is typi cal for the type of receive filters/transformers employed. normal 10base t compatible receive thresholds are employed when the lrt bit (csr15, bit 9) is cleared to zero. when the lrt bit is set to one, the low receive threshold option is invoked, and the sensitivity of the t mau receiver is increased. this allows longer line lengths to be employed, exceeding the 100 m target dis tance of normal 10base t (assuming typical 24 awg cable). the increased receiver sensitivity compensates for the increased signal attenuation caused by the addi tional cable distance. however, making the receiver more sensitive means that it is also more susceptible to extraneous noise, pri marily caused by coupling from co resident services (crosstalk). for this reason, it is recommended that when using the low receive threshold option that the service should be installed on 4 pair cable only. amd p r e l i m i n a r y 86 AM79C970A multipair cables within the same outer sheath have lower crosstalk attenuation, and may allow noise emit ted from adjacent pairs to couple into the receive pair, and be of sufficient amplitude to falsely unsquelch the t mau. link test function the link test function is implemented as specified by the 10base t standard. during periods of transmit pair inactivity, link beat pulses" will be periodically sent over the twisted pair medium to constantly monitor medium integrity. when the link test function is enabled (dlnktst bit in csr15 is cleared), the absence of link beat pulses and receive data on the rxd pair will cause the t mau to go into a link fail state. in the link fail state, data trans mission, data reception, data loopback and the collision detection functions are disabled, and remain disabled until valid data or more than five consecutive link pulses appear on the rxd pair. during link fail, the link status signal is inactive. when the link is identified as functional, the link status signal is asserted. the lnkst pin displays the link status signal by default. the t-mau will power up in the link fail state and the normal algorithm will apply to allow it to enter the link pass state. if t-mau is selected using the portsel bits in csr15, the t-mau will be forced into the link fail state when moving from aui to t-mau selection. transmission attempts during link fail state will pro- duce no network activity and will produce lcar and cerr error indications. in order to interoperate with systems which do not imple- ment link test, this function can be disabled by setting the dlnktst bit in csr15. with link test disabled, the data driver, receiver and loopback functions as well as collision detection remain enabled irrespective of the presence or absence of data or link pulses on the rxd pair. link test pulses continue to be sent regardless of the state of the dlnktst bit. polarity detection and reversal the t mau receive function includes the ability to invert the polarity of the signals appearing at the rxd pair if the polarity of the received signal is reversed (such as in the case of a wiring error). this feature allows data frames received from a reverse wired rxd input pair to be corrected in the t mau prior to transfer to the mendec. the polarity detection function is activated following h_reset or link fail, and will reverse the re ceive polarity based on both the polarity of any previous link beat pulses and the polarity of subsequent frames with a valid end transmit delimiter (etd). when in the link fail state, the t mau will recognize link beat pulses of either positive or negative polarity. exit from the link fail state is made due to the reception of 5-6 consecutive link beat pulses of identical polarity. on entry to the link pass state, the polarity of the last 5 link beat pulses is used to determine the initial receive polarity configuration and the receiver is reconfigured to subsequently recognize only link beat pulses of the pre viously recognized polarity. positive link beat pulses are defined as received signal with a positive amplitude greater than 585 mv (lrt = 1) with a pulse width of 60 ns-200 ns. this positive excur sion may be followed by a negative excursion. this defi nition is consistent with the expected received signal at a correctly wired receiver, when a link beat pulse which fits the template of figure 14 12 of the 10base t stan dard is generated at a transmitter and passed through 100 m of twisted pair cable. negative link beat pulses are defined as received sig nals with a negative amplitude greater than 585 mv with a pulse width of 60-200 ns. this negative excursion may be followed by a positive excursion. this definition is consistent with the expected received signal at a re verse wired receiver, when a link beat pulse which fits the template of figure 14 12 in the 10base t standard is generated at a transmitter and passed through 100 m of twisted pair cable. the polarity detection/correction algorithm will remain armed" until two consecutive frames with valid etd of identical polarity are detected. when armed", the re ceiver is capable of changing the initial or previous po larity configuration based on the etd polarity. on receipt of the first frame with valid etd following h_reset or link fail, the t mau will utilize the inferred polarity information to configure its rxd input, regardless of its previous state. on receipt of a second frame with a valid etd with correct polarity, the detection/correction algorithm will lock in" the received polarity. if the second (or subsequent) frame is not de tected as confirming the previous polarity decision, the most recently detected etd polarity will be used as the default. note that frames with invalid etd have no effect on updating the previous polarity decision. once two consecutive frames with valid etd have been received, the t mau will disable the detection/correction algorithm until either a link fail condition occurs or h_reset is activated. during polarity reversal, an internal pol signal will be active. during normal polarity conditions, this internal pol signal is inactive. the state of this signal can be read by software and/or displayed by led when enabled by the led control bits in the bus configuration registers (bcr4 to bcr7). twisted pair interface status when the t mau is in link pass state, three signals (xmt, rcv and col) indicate whether the t mau is p r e l i m i n a r y amd 87 AM79C970A transmitting, receiving, or in a collision state with both functions active simultaneously. these signals are in ternal signals that can be programmed to appear on any of the led output pins. programming is done by writing to bcr4 to bcr7. in the link fail state, xmt, rcv and col are inactive. collision detection function activity on both twisted pair signals rxd and txd at the same time constitutes a collision, thereby causing the internal col signal to be activated. col will remain active until one of the two colliding signals changes from active to idle. however, transmission attempt in link fail state results in lcar and cerr indication. col stays active for 2 bit times at the end of a collision. signal quality error test function the signal quality error (sqe) test function (also called heartbeat) is disabled when the 10base t port is selected. jabber function the jabber function prevents the twisted pair transmit function of the t mau txd from being active for an ex cessive period of time (20 ms to 150 ms). this prevents any one node from disrupting the network due to a stuck on" or faulty transmitter. if this maximum transmit time is exceeded, the t mau transmitter circuitry is disabled, the jab bit is set (csr4, bit 1) and the col signal is asserted. once the transmit data stream is re moved, the t mau waits an unjab" time of 250 ms to 750 ms before it deasserts col and re enables the transmit circuitry. power down the t mau circuitry can be made to go into a power savings mode. the t mau will go into the power down mode when h_reset is active, when coma mode is ac tive, or when the t mau is not selected. refer to the section power savings modes" for descriptions of the various power down modes. any of the three conditions listed above resets the inter nal logic of the t mau and places the device into power down mode. in this mode, the twisted pair driver pins (txd , txp ) are driven low, and the internal t mau status signals ( lnkst , rcvpol, xmt, rcv and col) signals are inactive. after coming out of the power down mode, the t-mau will remain in the reset state for an additional 10 m s. im mediately after the reset condition is removed, the t mau will be forced into the link fail state. the t mau will move to the link pass state only after 5-6 link beat pulses and/or a single received message is detected on the rd pair. in snooze mode, the t mau receive circuitry will remain enabled even while the sleep pin is driven low. 10base-t interface connection the figure below shows the proper 10base-t network interface design. refer to appendix a for a list of com- patible 10base-t filter/transformer modules. note that the recommended resistor values and filter and transformer modules are the same as those used by the imr+ (am79c981). xmt filter rcv filter rj45 connector filter & transformer module txp+ txd- txp- txd+ rxd+ rxd- pcnet?ci ii td+ td- rd+ rd- 1 2 3 6 61.9 w 422 w 61.9 w 422 w 100 w 1.21 k w 1:1 1:1 19436a 41 figure 38. 10base t interface connection amd p r e l i m i n a r y 88 AM79C970A full duplex operation the pcnet pci ii controller supports full duplex opera tion on all three network interfaces: aui, 10base t, and gpsi. full duplex operation allows simultaneous trans mit and receive activity on the txd and rxd pairs of the 10base t port, the do and di pairs of the aui port, or the txdat and rxdat pins of the gpsi port. full duplex operation is enabled by the fden and auifd bits located in bcr9. when operating in full du plex mode, the following changes to the device opera tion are made: bus interface/buffer management unit changes: n the first 64 bytes of every transmit frame are not pre served in the transmit fifo during transmission of the first 512 bits as described in the section trans mit exception conditions". instead, when full duplex mode is active and a frame is being transmitted, the xmtfw bits (csr80, bits 9-8) always govern when transmit dma is requested. n successful reception of the first 64 bytes of every re ceive frame is not a requirement for receive dma to begin as described in the section receive excep tion condition". instead, receive dma will be re quested as soon as either the receive fifo watermark (csr80, bits 13-12) is reached or a complete valid receive frame is detected, regardless of length. this receive fifo operation is identical to when the rpa bit (csr124, bit 3) is set during half duplex mode operation. mac engine changes: n changes to the transmit deferral mechanism: - transmission is not deferred while receive is active. - the inter packet gap (ipg) counter which gov erns transmit deferral during the ipg between back to back transmits is started when transmit activity for the first packet ends instead of when transmit and carrier activity ends. n when the aui or gpsi port is active, loss of carrier (lcar) reporting is disabled. (lcar is still reported when the 10base t port is active if a packet is trans mitted while in link fail state.) n the 4.0 m s carrier sense blinding period after a trans mission during which the sqe test normally occurs is disabled. n when the aui or gpsi port is active, the sqe test error reporting (cerr) is disabled. (cerr is still re ported when the 10base t port is active if a packet is transmitted while in link fail state.) n the collision indication input to the mac engine is ignored. t mau changes: n the internal transmit to receive feedback path which is used to indicate carrier sense during normal trans mission in half duplex mode is disabled. n the collision detect circuit is disabled. n the sqe test function is disabled. full duplex link status led support the pcnet pci ii controller provides a bit in each of the led status registers (bcr4, bcr5, bcr6, bcr7) to display the full duplex link status. if the fdlse bit (bit 8) is set, a value of one will be sent to the associ ated ledout bit when the t mau is in the full duplex link pass state. general purpose serial interface the general purpose serial interface (gpsi) provides a direct interface to the mac section of the pcnet pci ii controller. all signals are digital and data is non en coded. the gpsi allows use of an external manchester encoder/decoder such as the am7992b serial interface adapter (sia). in addition, it allows the pcnet pci ii controller to be used as a mac sublayer engine in a re peater designs based on the am79c981 imr+. gpsi mode is invoked by setting the gpsien bit (csr124, bit 4) to one and by selecting the interface through the portsel bits of the mode register (csr15, bits 8-7). the gpsi interface uses some of the same pins as the interface to the expansion rom. simultaneous use of both functions is not possible. reading from the expan sion rom and then reconfiguring the pins to the gpsi mode is supported. with this approach an external transceiver is required to prevent contention between the gpsi signals and the data outputs from the expan sion rom. eroe can be used as control signal for the external transceiver. after an h_reset all pins are internally configured to function as expansion rom interface. when the gpsi interface is selected by setting portsel (csr15, bits 8C7) to 10b, the pcnet-pci ii controller will terminate all further read accesses to expansion rom by asserting trdy within two clock cycles. the read data will be undefined. during the boot procedure the system will try to find an expansion rom. a pci system assumes that an expan- sion rom is present when it reads the rom signature 55h (byte 0) and aah (byte 1). a design without expan- sion rom can guarantee that the expansion rom de- tection fails by connecting two adjacent erd pins together. the recommended pins are pin 77 (erd6/txen) and pin 78 (erd5), since txen should have an external pull-down. gpsi signal functions are described in the pin descrip- tion section under the gpsi subheading. p r e l i m i n a r y amd 89 AM79C970A table 10. gpsi pin configuration pcnet pci ii pcnet pci ii pcnet pci ii controller c lance controller controller expansion gpsi function gpsi i/o type gpsi pin gpsi pin pin number rom pin collision i clsn clsn 81 erd3 receive clock i rclk rxclk 85 erd1 receive data i rx rxdat 86 erd0 receive enable i rena rxen 83 erd2 transmit clock i tclk txclk 80 erd4 transmit data o tx txdat 75 erd7 transmit enable o tena txen 77 erd6 note that the xtal1 input must always be driven with a clock source, even if gpsi mode is to be used. it is not necessary for the xtal1 clock to meet the normal fre quency and stability requirements in this case. any fre quency between 8 mhz and 20 mhz is acceptable. however, voltage drive requirements do not change. when gpsi mode is used, xtal1 must be driven for several reasons: n the default h_reset configuration for the pcnet pci ii controller is aui port selected and until gpsi mode is selected, the xtal1 clock is needed for some internal operations (namely, reset). n the xtal1 clock drives the eeprom read opera tion, regardless of the network mode selected. n the xtal1 clock determines the length the internal s_reset caused by the read of the reset register, regardless of the network mode. note that if a clock slower than 20 mhz is provided at the xtal1 input, the time needed for eeprom read and the internal s_reset will increase. external address detection interface the external address detection interface (eadi) is pro vided to allow external address filtering. it is selected by setting the eadisel bit in bcr2 to one. this feature is typically utilized for terminal servers, bridges and/or router products. the eadi interface can be used in con junction with external logic to capture the packet desti nation address from the serial bit stream as it arrives at the pcnet pci ii controller, compare the captured ad dress with a table of stored addresses or identifiers, and then determine whether or not the pcnet pci ii control ler should accept the packet. the eadi interface outputs are delivered directly from the nrz decoded data and clock recovered by the manchester decoder or input into the gpsi port. this al lows the external address detection to be performed in parallel with frame reception and address comparison in the mac station address detection (sad) block of the pcnet pci ii controller. srdclk is provided to allow clocking of the receive bit stream into the external address detection logic. note that when the 10base t port is selected, transitions on srdclk will only occur during receive activity. when the aui or gpsi port is selected, transitions on srdclk will occur during both transmit and receive activity. once a received frame commences and data and clock are available from the decoder, the eadi logic will monitor the alternating (1,0) preamble pattern until the two ones of the start frame delimiter (sfd, 10101011 bit pattern) are detected, at which point the sfbd output will be driven high. the sfbd signal will initially be low. the assertion of sfbd is a signal to the external address detection logic that the sfd has been detected and that subsequent srdclk cycles will deliver packet data to the external logic. therefore, when sfbd is asserted, the external address matching logic should begin de serialization of the srd data and send the resulting destination ad dress to a content addressable memory (cam) or other address detection device. in order to reduce the amount of logic external to the pcnet pci ii controller for multi ple address decoding systems, the sfbd signal will toggle at each new byte boundary within the packet, subsequent to the sfd. this eliminates the need for ex ternally supplying byte framing logic. srd is the decoded nrz data from the network. this signal can be used for external address detection. note that when the 10base t port is selected, transitions on srd will only occur during receive activity. when the aui or gpsi port is selected, transitions on srd will oc cur during both transmit and receive activity. the ear pin should be driven low by the external ad- dress comparison logic to reject a frame. if an address match is detected by comparison with either the physical address or logical address filter registers contained within the pcnet-pci ii controller or the frame is of the type broadcast, then the frame will be accepted regardless of the condition of ear . when amd p r e l i m i n a r y 90 AM79C970A the eadisel bit of bcr2 is set to one and the pcnet pci ii controller is programmed to promiscuous mode (prom bit of the mode register is set to one), then all incoming frames will be accepted, regardless of any ac tivity on the ear pin. internal address match is disabled when prom (csr15, bit 15) is cleared to zero, drcvbc (csr15, bit 14) and drcvpa (csr15, bit 13) are set to one and the logical address filter registers (csr8 to csr11) are programmed to all zeros. when the eadisel bit of bcr2 is set to one and inter- nal address match is disabled, then all incoming frames will be accepted by the pcnet-pci ii controller, unless the ear pin becomes active during the first 64 bytes of the frame (excluding preamble and sfd). this allows external address lookup logic approximately 58 byte times after the last destination address bit is available to generate the ear signal, assuming that the pcnet-pci ii controller is not configured to accept runt packets. the eadi logic only samples ear from 2 bit times after sfd until 512 bit times (64 bytes) after sfd. the frame will be accepted if ear has not been asserted during this win- dow. if runt packet accept (csr124, bit 3) is enabled, then the ear signal must be generated prior to the re- ceive message completion, if frame rejection is to be guaranteed. runt packet sizes could be as short as 12 byte times (assuming 6 bytes for source address, 2 bytes for length, no data, 4 bytes for fcs) after the last bit of the destination address is available. ear must have a pulse width of at least 110 ns. note that when the pcnet-pci ii controller is operating in full-duplex mode or runt packet accept is turned on (csr124, bit 3) the receive fifo watermark (csr80, bits 13C12) must be programmed to 64 (01b) or 128 (10b) to allow the full window of 512 bit times after sfd for the assertion of ear . if the watermark was pro- grammed to 16 (00b), receive fifo dma could start be- fore ear is asserted to reject the frame. the eadi outputs continue to provide data throughout the reception of a frame. this allows the external logic to capture frame header information to determine protocol type, inter-networking information, and other useful data. the eadi interface will operate as long as the strt bit in csr0 is set, even if the receiver and/or transmitter are disabled by software (dtx and drx bits in csr15 are set). this configuration is useful as a semi-power- down mode in that the pcnet-pci ii controller will not perform any power-consuming dma operations. how- ever, external circuitry can still respond to control frames on the network to facilitate remote node control. the table below summarizes the operation of the eadi interface: table 11. eadi operations prom ear required timing received messages 1 x no timing requirements all received frames 0 1 no timing requirements all received frames 0 0 low for 110 ns during the window from pcnet-pci ii controller internal physical 2 bits after sfd to 512 bits after sfd address and logical address filter matches and broadcast frames expansion rom interface the expansion rom is an 8-bit rom connected to the pcnet-pci ii controller expansion rom data bus (erd). it can be of up to 64 kbytes in size. the expan- sion rom address bus (era) is 8 bits wide. an external latch is required to store the upper 8 bits of the 16-bit ad- dress to the rom. all era outputs are forced to a con- stant level to conserve power while no access to the expansion rom is performed. eroe is asserted during the expansion rom read op- eration. this signal can be used to control the oe input of the rom. in an application that does not use the gpsi port, eroe can be left unconnected and the oe input of the rom can be tied to ground to always enable the rom data outputs. the ce input of the rom can either be tied to ground or it can also be connected to eroe. the signal eraclk is provided to strobe the upper 8 bits of the address into an external latch. the timing rela- tion of eraclk to era is such that both '373 (transpar- ent latch) and '374 (d flip-flop) types of address latch can be used. p r e l i m i n a r y amd 91 AM79C970A 19436a 42 pcnet?ci ii eroe eraclk era[7:0] erd[7:0] expansion rom ce oe a[15:8] a[7:0] d[7:0] latch figure 39. expansion rom interface the pcnet pci ii controller will always read four bytes for every host expansion rom read access. the inter face to the expansion rom runs synchronous to the pci bus interface clock. the pcnet pci ii controller will start the read operation to the expansion rom by driv ing the upper 8 bits of the expansion rom address on era[7:0]. this happens in the same clock cycle that the device claims the transfer by asserting devsel . one clock later, eroe is asserted and eraclk goes high to allow latching of the upper address bits externally. the upper portion of the expansion rom address will be the same for all four byte read cycles. eraclk is asserted for one clock. era[7:0] are driven with the upper 8-bits of the expansion rom address for one more clock cycle after eraclk goes low. next, the pcnet-pci ii control- ler starts driving the lower 8 bits of the expansion rom address on era[7:0]. the time the pcnet-pci ii controller waits for data to be valid is programmable. romtmg (bcr18, bits 15C12) defines the time from when the pcnet-pci ii controller drives era[7:0] with the lower 8-bits of the expansion rom address to when the pcnet-pci ii controller latches in the data on the erd[7:0] inputs. the register value specifies the time in number of clock cycles. when romtmg is set to nine (the default value), erd[7:0] is sampled with the next rising edge of clk nine clock cy- cles after era[7:0] was driven with a new address value. the clock edge that is used to sample the data is also the clock edge that generates the next expansion rom address. only the first three bytes of expansion rom data are stored in holding registers. the fourth byte is passed directly from the erd[7:0] inputs to the ad[31:24] outputs. one clock cycle after the last data byte is available, pcnet-pci ii controller asserts trdy . two clock cycles after the data is transferred on the pci bus, eroe is deasserted. the access time for the expansion rom device (t acc ) can be calculated by subtracting the clock to output de lay for the era[7:0] outputs (t val (era)) and the input to clock setup time for the erd[7:0] inputs (t su (erd)) from the time defined by romtmg: t acc romtmg* clock period - t val (era) - t su (erd) for an adapter card application, the value used for clock period should be 30 ns to guarantee correct interface timing at the maximum clock frequency of 33 mhz. amd p r e l i m i n a r y 92 AM79C970A the timing diagram below assumes the default pro gramming of romtmg (1001b = 9 clk). after reading the first byte, the pcnet pci ii controller reads in three more bytes by incrementing the lower portion of the rom address. after the last byte is strobed in, trdy will be asserted on clock 44. when the host tries to perform a burst read of the expansion rom, the pcnet-pci ii will disconnect the access at the second data phase. 19436a-43 frame ad c/ be par irdy trdy devsel stop era erd eroe eraclk clk 1234567891011121314151617181920 a[15:8] a[7:2],0,0 a[7:2],0,1 frame ad c/ be par irdy trdy devsel stop era erd eroe eraclk clk 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 21 22 23 44 45 a[7:2],1,0 a[7:2],1,1 figure 40. expansion rom bus read sequence the host must program the expansion rom base ad dress register in the pci configuration space before the first access to the expansion rom. the pcnet pci ii controller will not react to any access to the expansion rom until both memen (pci command register, bit 1) and romen (pci expansion rom base address regis ter, bit 0) are set to one. after the expansion rom is enabled, the pcnet pci ii controller will claim all mem ory read accesses with an address between rombase and rombase + 64k - 4 (rombase, pci expansion rom base address register, bits 31-11). the address output to the expansion rom is the offset from the ad dress on the pci bus to rombase. the pcnet pci ii controller aliases all accesses to the expansion rom of the command types memory read multiple" and mem ory read line" to the basic memory read command. since setting memen also enables memory mapped access to the i/o resources, attention must be given to the pci memory mapped i/o base address register, be fore enabling access to the expansion rom. the host must set the pci memory mapped i/o base address p r e l i m i n a r y amd 93 AM79C970A register to a value that prevents the pcnet pci ii controller from claiming any memory cycles not in tended for it. the expansion rom interface uses some of the same pins as the gpsi interface. simultaneous use of both functions is not possible. reading from the expansion rom and then reconfiguring the pins to the gpsi mode is supported. an external transceiver is required to pre vent contention between the gpsi signals and the data outputs from the expansion rom. eroe can be used as control signal for the external transceiver. after an h_reset all pins are internally configured to function as expansion rom interface. when the gpsi interface is selected by setting portsel (csr15, bits 8C7) to 10b, the pcnet-pci ii controller will terminate all further read accesses to expansion rom by assert- ing trdy within two clock cycles. the read data will be undefined. during the boot procedure the system will try to find an expansion rom. a pci system assumes that an expansion rom is present when it reads the rom sig- nature 55h (byte 0) and aah (byte 1). a design without expansion rom can guarantee that the expansion rom detection fails by connecting two adjacent erd pins together and tying them high or low. eeprom microwire interface the pcnet-pci ii controller contains a built-in capability for reading and writing to an external serial eeprom. this built-in capability consists of an interface for direct connection to a microwire compatible eeprom, an automatic eeprom read feature, and a user-program- mable register that allows direct access to the microwire interface pins. automatic eeprom read operation shortly after the deassertion of the rst pin, the pcnet-pci ii controller will read the contents of the eeprom that is attached to the microwire interface. because of this automaticread capability of the pcnet- pci ii controller, an eeprom can be used to program many of the features of the pcnet-pci ii controller at power-up, allowing system-dependent configuration in- formation to be stored in the hardware, instead of inside the device driver. if an eeprom exists on the microwire interface, the pcnet-pci ii controller will read the eeprom contents at the end of the h_reset operation. the eeprom contents will be serially shifted into a temporary register and then sent to various register locations on board the pcnet-pci ii controller. access to the pcnet-pci ii con- troller configuration space, the expansion rom or any i/o resource is not possible during the eeprom read operation. the pcnet-pci ii controller will terminate any access attempt with the assertion of devsel and stop while trdy is not asserted, signaling to the initia- tor to disconnect and retry the access at a later time. a checksum verification is performed on the data that is read from the eeprom. if the checksum verification passes, pvalid (bcr19, bit 15) will be set to one. if the checksum verification of the eeprom data fails, pvalid will be cleared to zero and the pcnet-pci ii controller will force all eeprom-programmable bcr registers back to their h_reset default values. the content of the address prom locations (offsets 0hCfh from the i/o or memory mapped i/o base address), however, will not be cleared. the 8 bit checksum for the entire 36 bytes of the eeprom should be ffh. if no eeprom is present at the time of the automatic read operation, the pcnet-pci ii controller will recog- nize this condition and will abort the automatic read op- eration and clear both the pread and pvalid bits in bcr19. all eeprom-programmable bcr registers will be assigned their default values after h_reset. the content of the address prom locations (offsets 0hCfh from the i/o or memory mapped i/o base address) will be undefined. if the user wishes to modify any of the configuration bits that are contained in the eeprom, then the seven com- mand, data and status bits of bcr19 can be used to write to the eeprom. after writing to the eeprom, the host should set the pread bit of bcr19. this action forces a pcnet-pci ii controller re-read of the eeprom so that the new eeprom contents will be loaded into the eeprom-programmable registers on board the pcnet-pci ii controller. (the eeprom-programmable registers may also be reprogrammed directly, but only information that is stored in the eeprom will be pre- served at system power-down.) when the pread bit of bcr19 is set, it will cause the pcnet-pci ii controller to ignore further accesses to the pcnet-pci ii controller configuration space, the expansion rom, or any i/o re- source until the completion of the eeprom read opera- tion. the pcnet-pci ii controller will terminate these access attempts with the assertion of devsel and stop while trdy is not asserted, signaling to the initia- tor to disconnect and retry the access at a later time. eeprom auto-detection the pcnet-pci ii controller uses the eesk/ led1 /sfbd pin to determine if an eeprom is present in the system. at the rising edge of clk during the last clock during which rst is asserted, the pcnet-pci ii controller will sample the value of the eesk/ led1 /sfbd pin. if the sampled value is a one, then the pcnet-pci ii control- ler assumes that an eeprom is present, and the eeprom read operation begins shortly after the rst pin is deasserted. if the sampled value of eesk/ led1 /sfbd is a zero, the pcnet-pci ii amd p r e l i m i n a r y 94 AM79C970A controller assumes that an external pulldown device is holding the eesk/ led1 /sfbd pin low indicating that there is no eeprom in the system. note that if the de- signer creates a system that contains an led circuit on the eesk/ led1 /sfbd pin but has no eeprom pre- sent, then the eeprom auto-detection function will in- correctly conclude that an eeprom is present in the system. however, this will not pose a problem for the pcnet-pci ii controller, since the checksum verification will fail. direct access to the microwire interface the user may directly access the microwire port through the eeprom register, bcr19. this register contains bits that can be used to control the microwire interface pins. by performing an appropriate sequence of ac- cesses to bcr19, the user can effectively write to and read from the eeprom. this feature may be used by a system configuration utility to program hardware con- figuration information into the eeprom. eeprom-programmable registers the following registers contain configuration informa- tion that will be programmed automatically during the eeprom read operation: n i/o offsets 0h-fh address prom locations n bcr2 miscellaneous configuration register n bcr4 link status led register n bcr5 led1 status register n bcr6 led2 status register n bcr7 led3 status register n bcr9 full duplex control register n bcr18 burst and bus control register n bcr22 pci latency register if pread (bcr19, bit 14) and pvalid (bcr19, bit 15) are cleared to zero, then the eeprom read has experienced a failure and the contents of the eeprom programmable bcr register will be set to default h_reset values. the content of the address prom locations, however, will not be cleared. note that accesses to the address prom i/o locations do not directly access the address eeprom itself. in stead, these accesses are routed to a set of shadow reg isters on board the pcnet pci ii controller that are loaded with a copy of the eeprom contents during the automatic read operation that immediately follows the h_reset operation. p r e l i m i n a r y amd 95 AM79C970A eeprom map the automatic eeprom read operation will access 18 words (i.e. 36 bytes) of the eeprom. the format of the eeprom contents is shown below, beginning with the byte that resides at the lowest eeprom address: table 12. eeprom content word byte byte address addr. most significant byte addr. least significant byte 00h 01h second byte of the iso 8802 3 00h first byte of the iso 8802 3 (lowest (ieee/ansi 802.3) station physical (ieee/ansi 802.3) station physical eeprom address for this node address for this node, where first byte address) refers to the first byte to appear on the 802.3 medium 01h 03h fourth byte of the node address 02h third byte of the node address 02h 05h sixth byte of the node address 04h fifth byte of the node address 03h 07h reserved location: must be 00h 06h reserved location must be 00h 04h 09h hardware id: must be 11h if compatibility 08h reserved location must be 00h to amd drivers is desired 05h 0bh user programmable space 0ah user programmable space 06h 0dh msbyte of two byte checksum, which is the 0ch lsbyte of two byte checksum, which is the sum of bytes 00h-0bh and bytes is the sum of bytes 00h-0bh and bytes 0eh and 0fh 0eh and 0fh 07h 0fh must be ascii w (57h) if compatibility to 0eh must be ascii w (57h) if compatibility to amd driver software is desired amd driver software is desired 08h 11h bcr4[15:8] (link status led) 10h bcr4[7:0] (link status led) 09h 13h bcr5[15:8] (led1 status) 12h bcr5[7:0] (led1 status) 0ah 15h bcr18[15:8] (burst and bus control) 14h bcr18[7:0] (burst and bus control) 0bh 17h bcr2[15:8] (miscellaneous configuration) 16h bcr2[7:0] (miscellaneous configuration) 0ch 19h bcr6[15:8] (led2 status) 18h bcr6[7:0] (led2 status) 0dh 1bh bcr7[15:8] (led3 status) 1ah bcr7[7:0] (led3 status) 0eh 1dh bcr9[15:8] (full duplex control) 1ch bcr9[7:0] (full duplex control) 0fh 1fh checksum adjust byte for the first 36 bytes 1eh reserved location must be 00h of the eeprom contents, checksum of the first 36 bytes of the eeprom should total to ffh 10h 21h bcr22[15:8] (pci latency) 20h bcr22[7:0] (pci latency) 11h 23h reserved location must be 00h 22h reserved location must be 00h note that the first bit out of any word location in the eeprom is treated as the msb of the register that is be ing programmed. for example, the first bit out of eeprom word location 08h will be written into bcr4, bit 15, the second bit out of eeprom word location 08h will be written into bcr4, bit 14, etc. there are two checksum locations within the eeprom. the first checksum will be used by amd driver software to verify that the iso 8802 3 (ieee/ansi 802.3) station address has not been corrupted. the value of bytes 0ch and 0dh should match the sum of bytes 00h through 0bh and 0eh and 0fh. the second checksum location byte 21h is not a checksum total, but is, instead, a checksum adjustment. the value of this byte should be such that the total checksum for the entire 36 bytes of eeprom data equals the value ffh. the checksum adjust byte is needed by the pcnet pci ii controller in order to verify that the eeprom content has not been corrupted. led support the pcnet pci ii controller can support up to four leds. led outputs lnkst , led1 and led2 allow for direct connection of an led and its supporting pullup device. led output led3 may require an additional buffer between the pcnet-pci ii controller output pin and the led and its supporting pullup device. because the led3 output is multiplexed with other pcnet-pci ii controller functions, it may not always be possible to connect an led circuit directly to the led3 pin. in applications that want to use the pin to drive an amd p r e l i m i n a r y 96 AM79C970A led and also have an eeprom, it might be necessary to buffer the led3 circuit from the eeprom connection. when an led circuit is directly connected to the eedo/ led3 /srd pin, then it is not possible for most microwire eeprom devices to sink enough i ol to maintain a valid low level on the eedo input to the pcnet-pci ii controller. in applications where an eeprom is not needed, the led3 pin may be directly connected to an led circuit. the pcnet-pci ii controller led3 pin driver will be able to sink enough current to properly drive the led circuit. each led can be programmed through a bcr register to indicate one or more of the following network status or activities: collision status, full-duplex link status, half-duplex link status, jabber status, magic packet status, receive match, receive polarity, receive status and transmit status. the led pins can be con- figured to operate in either open-drain mode (active low) or in totem-pole mode (active high). the output can be stretched to allow the human eye to recognize even short events that last only several microseconds. after h_reset, the four led outputs are configured in the following manner: table 13. led default configuration led output indication driver mode pulse stretch lnkst link status open drain C active low enabled led1 receive status open drain C active low enabled led2 receive polarity open drain C active low enabled led3 transmit status open drain C active low enabled for each led register, each of the status signals is anded with its enable signal, and these signals are all ored together to form a combined status signal. each led pins combined status signal can be programmed to run to a pulse stretcher, which consists of a 3-bit shift register clocked at 38 hz (26 ms). the data input of each shift register is normally at logic 0. the or gate output for each led register asynchronously sets all three bits of its shift register when the output becomes asserted. the inverted output of each shift register is used to con- trol an led pin. thus the pulse stretcher provides 2C3 clocks of stretched led output, or 52 ms to 78 ms. 19436a-44 col cole fdls fdlse jab jabe lnkst lnkste rcv rcve rcvm rcvme rxpol rxpole xmt xmte to pulse stretch mfs mfse figure 41. led control logic p r e l i m i n a r y amd 97 AM79C970A power savings modes the pcnet pci ii controller supports two hardware power savings modes. both are entered by driving the sleep pin low. the power down mode that yields the most power sav- ings is called coma mode. in coma mode, the entire device is shut down. all inputs are ignored except the sleep pin itself. coma mode is enabled when awake (bcr2, bit 2) is at its default value of zero and sleep is asserted. the second power saving mode is called snooze mode. in snooze mode, enabled by setting awake to one and driving the sleep pin low, the t-mau receive cir- cuitry will remain active even while the sleep pin is driven low. the lnkst output is the only one of the led pins that continues to function. all other sections of the device are shut down. the lnkste bit must be set in bcr4 to enable indication of a good 10base-t link if there are link beat pulses or valid frames present. this lnkst pin can be used to drive an led and/or external hardware that directly controls the sleep pin of the pcnet-pci ii controller. this configuration effectively wakes the system when there is any activity on the 10base-t link. snooze mode can be used only if the t-mau is the selected network port. link beat pulses are not transmitted during snooze mode. the sleep pin must not be asserted while the pcnet- pci ii controller is requesting the bus or while a slave or bus master cycle is in progress. a recommended method is to set the pcnet-pci ii controller into suspend mode by setting the spnd bit in csr5 to one prior to asserting the sleep pin. another recom- mended method is to stop the device by setting the stop bit in csr0 to one prior to asserting the sleep pin. before the sleep mode is invoked, the pcnet-pci ii controller will perform an internal s_reset. this s_reset operation will not affect the values of the bcr registers or the pci configuration space. s_reset ter- minates all network activity abruptly. the host can use the suspend mode (spnd, csr5, bit 0) to terminate all network activity in an orderly sequence before issuing an s_reset. when coming out of the sleep mode, the pcnet-pci ii controller can be programmed to generate an interrupt and inform the driver about the wake-up. the pcnet-pci ii controller will set slpint (csr5, bit 9), when coming out of the sleep mode. inta will be asserted, when the enable bit slpinte (csr5, bit 8) is set to one. note that the assertion of inta due to slpint is not dependent on the main interrupt enable bit inea (csr0, bit 6), which will be cleared by the reset going into the sleep mode. the sleep pin should not be asserted during power supply ramp-up. if it is desired that sleep be asserted at power up time, then the system must delay the asser- tion of sleep until three clock cycles after the comple- tion of a hardware reset operation. ieee 1149.1 test access port interface an ieee 1149.1 compatible boundary scan test access port is provided for board level continuity test and diag- nostics. all digital input, output and input/output pins are tested. analog pins, including the aui differential driver (do ) and receivers (di , ci ), and the crystal input (xtal1/xtal2) pins, are not tested. the t mau drivers txd , txp and receiver rxd are also not tested. the following is a brief summary of the ieee 1149.1 compatible test functions implemented in the pcnet pci ii controller. boundary scan circuit the boundary scan test circuit requires four pins (tck, tms, tdi and tdo), defined as the test access port (tap). it includes a finite state machine (fsm), an in struction register, a data register array, and a power on reset circuit. internal pull up resistors are provided for the tdi, tck, and tms pins. the boundary scan circuit remains active during sleep mode. tap finite state machine the tap engine is a 16 state finite state machine (fsm), driven by the test clock (tck) and the test mode select (tms) pins. an independent power on reset circuit is provided to ensure the fsm is in the test_logic_reset state at power up. the fsm is also reset when tms and tdi are high for five tck periods. supported instructions in addition to the minimum ieee 1149.1 requirements (bypass, extest, and sample instructions), three additional instructions (idcode, tribyp and setbyp) are provided to further ease board level test ing. all unused instruction codes are reserved. see the following table for a summary of supported instructions. amd p r e l i m i n a r y 98 AM79C970A table 14. ieee 1149.1 supported instruction summary instruction name instruction code description mode selected data register extest 0000 external test test bsr idcode 0001 id code inspection normal id reg sample 0010 sample boundary normal bsr tribyp 0011 force float normal bypass setbyp 0100 control boundary to 1/0 test bypass bypass 1111 bypass scan normal bypass instruction register and decoding logic after the tap fsm is reset, the idcode instruction is always invoked. the decoding logic gives signals to control the data flow in the data registers according to the current instruction. boundary scan register each boundary scan register (bsr) cell has two stages. a flip flop and a latch are used for the serial shift stage and the parallel output stage, respectively. there are four possible operation modes in the bsr cell: table 15. boundary scan register mode of operation 1 capture 2 shift 3 update 4 system function other data registers 1. bypass register (1 bit) 2. device id register (32 bits) table 16. device id register bits 31-28 version bits 27-12 part number (0010 0100 0011 xxxx) bits 11-1 manufacturer id. the 11 bit manufacturer id cod for amd is 00000000001 in accordance with jedec publication 106 a. bit 0 always a logic 1 note that the content of the device id register is the same as the content of csr88. p r e l i m i n a r y amd 99 AM79C970A nand tree testing the pcnet pci ii controller provides a nand tree test mode to allow checking connectivity to the device on a printed circuit board. the nand tree is built on all pci bus signals. nand tree testing is enabled by asserting rst . all pci bus signals will become inputs on the assertion of rst . the result of the nand tree test can be observed on the nout pin. 19436a-45 pcnet-pci ii core rst (pin 120) inta (pin 117) vdd clk (pin 121) ad0 (pin 57) nout (pin 62) b a s mux o vdd figure 42. nand tree circuitry amd p r e l i m i n a r y 100 AM79C970A pin 120 ( rst ) is the first input to the nand tree. pin 117 ( inta ) is the second input to the nand tree, followed by pin 121 (clk). all other pci bus signals follow, counter- clockwise, with pin 57 (ad0) being the last. pins labeled nc and all power supply pins are not part of the nand tree. the table below shows the complete list of pins connected to the nand tree. table 17. nand tree pin sequence nand nand nand tree tree tree input no. pin no. name input no. pin no. name input no. pin no. name 1 120 rst 18 15 ad21 35 36 ad15 2 117 inta 19 16 ad20 36 38 ad14 3 121 clk 20 18 ad19 37 39 ad13 4 123 gnt 21 19 ad18 38 40 ad12 5 126 req 22 21 ad17 39 41 ad11 6 128 ad31 23 22 ad16 40 42 ad10 7 129 ad30 24 23 c/ be 2 41 44 ad9 8 131 ad29 25 24 frame 42 45 ad8 9 132 ad28 26 25 irdy 43 47 c/ be 0 10 2 ad27 27 26 trdy 44 48 ad7 11 3 ad26 28 27 devsel 45 49 ad6 12 5 ad25 29 28 stop 46 51 ad5 13 6 ad24 30 29 lock 47 52 ad4 14 7 c/ be 331 31 perr 48 53 ad3 15 10 idsel 32 32 serr 49 54 ad2 16 12 ad23 33 34 par 50 56 ad1 17 13 ad22 34 35 c/ be 1 51 57 ad0 rst must be asserted low to start a nand tree test se- quence. initially, all nand tree inputs except rst should be driven high. this will result in a high output at the nout pin. if the nand tree inputs are driven from high to low in the same order as they are connected to build the nand tree, nout will toggle every time an ad- ditional input is driven low. nout will change to low, when inta is driven low and all other nand tree inputs stay high. nout will toggle back to high, when clk is additionally driven low. the square wave will continue until all nand tree inputs are driven low. nout will be high, when all nand tree inputs are driven low. note, that some of the pins connected to the nand tree are outputs in normal mode of operation. they must not be driven from an external source until the pcnet-pci ii controller is configured for nand tree testing. p r e l i m i n a r y amd 101 AM79C970A rst inta clk gnt req ad[31:0] c/ be [3:0] idsel frame irdy trdy devsel stop lock perr serr par nout ffffffff 31 0000ffff f 7 19436a 47 figure 1. nand tree waveform reset there are three different types of reset operations that may be performed on the pcnet pci ii controller device, h_reset, s_reset and stop. these names have been used throughout the document. the follow ing is a description of each type of reset operation. h_reset hardware reset (h_reset) is a pcnet pci ii control ler reset operation that has been created by the proper assertion of the rst pin of the pcnet-pci ii controller device. when the minimum pulse width timing as speci- fied in the rst pin description has been satisfied, then an internal reset operation will be performed. h_reset will program most of the csr and bcr regis- ters to their default value. note that there are several csr and bcr registers that are undefined after h_reset. see the sections on the individual registers for details. h_reset will clear all registers in the pci configuration space. h_reset will cause the microcode program to jump to its reset state. following the end of the h_reset operation, the pcnet-pci ii controller will attempt to read the eeprom device through the eeprom microwire interface. h_reset resets the t-mau into the link fail state. s_reset software reset (s_reset) is a pcnet-pci ii controller reset operation that has been created by a read access to the reset register which is located at offset 14h in word i/o mode or offset 18h in dword i/o mode from the pcnet-pci ii controller i/o or memory mapped i/o base address. s_reset will reset all of or some portions of csr0, 3, 4, 15, 80, 100 and 124 to default values. for the identity of individual csrs and bit locations that are affected by s_reset, see the individual csr register descriptions. s_reset will not affect any pci configuration space locations. with the exception of dwio (bcr18, bit 7) s _reset will not affect any of the bcr register values. s_reset will cause the microcode program to jump to its reset state. following the end of the s_reset op- eration, the pcnet-pci ii controller will not attempt to read the eeprom device. s_reset does not affect the status of the t-mau. after s_reset, the host must perform a full re-initialization of the pcnet-pci ii control- ler before starting network activity. s_reset will clear dwio (bcr18, bit 7) and the pcnet-pci ii controller will be in 16-bit i/o mode after the reset operation. a dword write operation to the rdp (i/o offset 10h) must be performed to set the device into 32-bit i/o mode. s_reset will cause req to deassert immediately. stop (csr0, bit 2) or spnd (csr5, bit 0) can be used to terminate any pending bus mastership request in an orderly sequence. s_reset terminates all network activity abruptly. the host can use the suspend mode (spnd, csr5, bit 0) to amd p r e l i m i n a r y 102 AM79C970A terminate all network activity in an orderly sequence be fore issuing an s_reset. stop a stop reset is generated by the assertion of the stop bit in csr0. writing a one to the stop bit of csr0, when the stop bit currently has a value of zero, will in itiate a stop reset. if the stop bit is already a one, then writing a one to the stop bit will not generate a stop reset. stop will reset all or some portions of csr0, 3, and 4 to default values. for the identity of individual csrs and bit locations that are affected by stop, see the individual csr register descriptions. stop will not affect any of the bcr and pci configuration space locations. stop will cause the microcode program to jump to its reset state. following the end of the stop operation, the pcnet pci ii controller will not attempt to read the eeprom device. setting the stop bit does not affect the t mau. note that stop will not cause a deassertion of the req signal, if it happens to be active at the time of the write to csr0. the pcnet-pci ii controller will wait until it gains bus ownership and it will first finish all scheduled bus master accesses before the stop reset is executed. stop terminates all network activity abruptly. the host can use the suspend mode (spnd, csr5, bit 0) to ter- minate all network activity in an orderly sequence before setting the stop bit. software access pci configuration registers the pcnet-pci ii controller implements a 256-byte con- figuration space as defined by the pci specification revision 2.0. the 64-byte header includes all registers required to identify the pcnet-pci ii controller and its function. additional registers are used to setup the con- figuration of the pcnet-pci ii controller in a system. none of the device specific registers located at offsets 40h through fch are implemented. the layout of the pcnet-pci ii controller pci configuration space is shown in the table below. the pci configuration registers are accessible only by configuration cycles. all multi-byte numeric fields follow little endian byte ordering. all write accesses to re- served locations have no effect; reads from these loca- tions will return a data value of zero. table 18. pci configuration space layout device id vendor id 00h status command 04h base-class sub-class programming if revision id 08h reserved header type latency timer reserved 0ch i/o base address 10h memory mapped i/o base address 14h reserved 18h reserved 1ch reserved 20h reserved 24h reserved 28h reserved 2ch expansion rom base address 30h reserved 34h reserved 38h max_lat min_gnt interrupt pin interrupt line 3ch reserved 40h reserved reserved fch 31 24 23 16 15 8 7 0 offset . . p r e l i m i n a r y amd 103 AM79C970A i/o resources the pcnet pci ii controller requires 32 bytes of address space for access to all the various internal registers as well as to some setup information stored in an external serial eeprom. a software reset port is available, too. the pcnet pci ii controller supports mapping the ad dress space to both i/o and memory space. the value in the pci i/o base address register determines the start address of the i/o address space. the register is typi cally programmed by the pci configuration utility after system power up. the pci configuration utility must also set the ioen bit in the pci command register to en able i/o accesses to the pcnet pci ii controller. for memory mapped i/o access, the pci memory mapped i/o base address register controls the start address of the memory space. the memen bit in the pci com mand register must also be set to enable the mode. both base address registers can be active at the same time. the pcnet pci ii controller supports two modes for ac cessing the i/o resources. for backwards compatibility with amd's 16 bit ethernet controllers, word i/o is the default mode after power up. the device can be config ured to dword i/o mode by software. i/o registers the pcnet pci ii controller registers are divided into two groups. the control and status registers (csr) are used to configure the ethernet mac engine and to obtain status information. the bus control registers (bcr) are use to configure the bus interface unit and the leds. both sets of registers are accessed using indirect addressing. the csr and bcr share a common register address port (rap). there are, however, separate data ports. the register data port (rdp) is used to access a csr. the bcr data port (bdp) is used to access a bcr. in order to access a particular csr location, the rap should first be written with the appropriate csr ad dress. the rdp will then points to the selected csr. a read of the rdp will yield the selected csr data. a write to the rdp will write to the selected csr. in order to ac cess a particular bcr location, the rap should first be written with the appropriate bcr address. the bdp will then points to the selected bcr. a read of the bdp will yield the selected bcr data. a write to the bdp will write to the selected bcr. once the rap has been written with a value, the rap value remains unchanged until another rap write oc curs, or until an h_reset or s_reset occurs. rap is cleared to all zeros when an h_reset or s_reset occurs. rap is unaffected by setting the stop bit. address prom space the pcnet pci ii controller allows for connection of a serial eeprom. the first 16 bytes of the eeprom will be automatically loaded into the address prom (aprom) space after h_reset. the address prom space is a convenient place to store the value of the 48 bit ieee station address. it can be overwritten by the host computer. its content has no effect on the operation of the controller. the software must copy the station ad dress from the address prom space to the initialization block or to csr12 14 in order for the receiver to accept unicast frames directed to this station. the 6 bytes of ieee station address occupy the first 6 locations of the address prom space. the next six bytes are reserved. bytes 12 and 13 should match the value of the checksum of bytes 1 through 11 and 14 and 15. bytes 14 and 15 should each be ascii w (57h). the above requirements must be met in order to be compat ible with amd driver software. the apromwe bit (bcr2, bit 8) must be set to one to enable write access to the address prom space. reset register a read of the reset register creates an internal software reset (s_reset) pulse in the pcnet pci ii controller. the internal s_reset pulse that is generated by this access is different from both the assertion of the hardware rst pin (h_reset) and from the assertion of the software stop bit. specifically, s_reset is the equivalent of the assertion of the rst pin (h_reset) except that s_reset has no effect on the bcr or pci configuration space locations or on the t-mau. the ne2100 lance based family of ethernet cards requires that a write access to the reset register follows each read access to the reset register. the pcnet-pci ii controller does not have a similar require- ment. the write access is not required but it does not have any effects. note that the pcnet-pci ii controller cannot service any slave accesses for a very short time after a read access of the reset register, because the internal s_reset operation takes about 1 m s to finish. the pcnet pci ii controller will terminate all slave accesses with the as sertion of devsel and stop while trdy is not as- serted, signaling to the initiator to disconnect and retry the access at a later time. word i/o mode after h_reset, the pcnet-pci ii controller is pro- grammed to operate in word i/o mode. dwio (bcr18, bit 7) will be cleared to zero. the table below shows how the 32 bytes of address space are used in word i/o mode. amd p r e l i m i n a r y 104 AM79C970A table 19. i/o map in word i/o mode (dwio = 0) offset no. of bytes register 00h - 0fh 16 aprom 10h 2 rdp 12h 2 rap (shared by rdp and bdp) 14h 2 reset register 16h 2 bdp 18h - 1fh 8 reserved all i/o resources must be accessed in word quantities and on word addresses. the address prom locations can also be read in byte quantities. the only allowed dword operation is a write access to the rdp, which switches the device to dword i/o mode. a read access other than listed in the table below will yield undefined data, a write operation may cause unex pected reprogramming of the pcnet pci ii controller control registers. table 20. legal i/o accesses in word i/o mode (dwio = 0) ad[4:0] be [3:0] type comment 0xx00 1110 rd byte read of aprom location 0h, 4h, 8h or ch 0xx01 1101 rd byte read of aprom location 1h, 5h, 9h or dh 0xx10 1011 rd byte read of aprom location 2h, 6h, ah or eh 0xx11 0111 rd byte read of aprom location 3h, 7h, bh or fh 0xx00 1100 rd word read of aprom locations 1h (msb) and 0h (lsb), 5h and 4h, 8h and 9h or ch and dh 0xx10 0011 rd word read of aprom locations 3h (msb) and 2h (lsb), 7h and 6h, bh and ah or fh and eh 10000 1100 rd word read of rdp 10010 0011 rd word read of rap 10100 1100 rd word read of reset register 10110 0011 rd word read of bdp 0xx00 1100 wr word write to aprom locations 1h (msb) and 0h (lsb), 5h and 4h, 8h and 9h or ch and dh 0xx10 0011 wr word write to aprom locations 3h (msb) and 2h (lsb), 7h and 6h, bh and ah or fh and eh 10000 1100 wr word write to rdp 10010 0011 wr word write to rap 10100 1100 wr word write to reset register 10110 0011 wr word write to bdp 10000 0000 wr dword write to rdp, switches device to dword i/o mode double word i/o mode the pcnet-pci ii controller can be configured to oper- ate in dword (32bit) i/o mode. the software can invoke the dwio mode by performing a dword write access to the i/o location at offset 10h (rdp). the data of the write access must be such that it does not affect the intended operation of the pcnet-pci ii controller. setting the de- vice into 32-bit i/o mode is usually the first operation af- ter h_reset or s_reset. the rap register will point to csr0 at that time. writing a value of zero to csr0 is a save operation. dwio (bcr18, bit 7) will be set to one as indicating that the pcnet-pci ii controller oper- ates in 32-bit i/o mode. note that even though the i/o resource mapping changes when the i/o mode setting changes, the rdp location offset is the same for both modes. once the dwio bit has been set to one, only h_reset or s_reset can clear it to zero. the dwio mode set- ting is unaffected by setting the stop bit. the table below shows how the 32 bytes of address space are used in dword i/o mode. p r e l i m i n a r y amd 105 AM79C970A table 21. i/o map in dword i/o mode (dwio = 1) offset no. of bytes register 00h - 0fh 16 aprom 10h 4 rdp 14h 4 rap (shared by rdp and bdp) 18h 4 reset register 1ch 4 bdp all i/o resources must be accessed in dword quantities and on dword addresses. a read access other than listed in the table below will yield undefined data, a write operation may cause unexpected reprogramming of the pcnet pci ii controller control registers. table 22. legal i/o accesses in double word i/o mode (dwio = 1) ad[4:0] be [3:0] type comment 0xx00 0000 rd dword read of aprom locations 3h (msb) to 0h (lsb), 7h to 4h, bh to 8h or fh to ch 10000 0000 rd dword read of rdp 10100 0000 rd dword read of rap 11000 0000 rd dword read of reset register 0xx00 0000 wr dword write to aprom locations 3h (msb) to 0h (lsb), 7h to 4h, bh to 8h or fh to ch 10000 0000 wr dword write to rdp 10100 0000 wr dword write to rap 11000 0000 wr dword write to reset register user accessible registers the pcnet-pci ii controller has three types of user registers: the pci configuration registers, the control and status registers (csr) and the bus control registers (bcr). the pcnet-pci ii controller implements all pcnet-isa (am79c960) registers, all c-lance (am79c90) regis- ters, all ilacc (am79c900) registers, plus a number of additional registers. the pcnet-pci ii controller csrs are compatible with both the pcnet-isa csrs and all of the c-lance csrs upon power up. compatibility to the ilacc set of csrs requires one access to the software style register (bcr20, bits 7C0) to be performed. by setting an appropriate value of the software style regis- ter (bcr20, bits 7C0) the user can select a set of csrs that are compatible with the ilacc set of csrs. the pci configuration registers can be accessed in any data width. all other registers must be accessed accord- ing to the i/o mode that is currently selected. when wio mode is selected, all other register locations are defined to be 16 bits in width. when dwio mode is selected, all these register locations are defined to be 32 bits in width, with the upper 16 bits of most register locations marked as reserved locations with undefined values. when performing register write operations in dwio mode, the upper 16 bits should always be written as zeros. when performing register read operations in dwio mode, the upper 16 bits of i/o resources should always be regarded as having undefined values, except for csr88. pcnet-pci ii controller registers can be divided into four groups: pci configuration registers registers that are intended to be initialized by the system initialization procedure (e.g. bios device initialization routine) to program the operation of the pcnet-pci ii controller pci bus interface. setup registers registers that are intended to be initialized by the device driver to program the operation of various pcnet-pci ii controller features. running registers registers that are intended to be used by the device driver software once the pcnet-pci ii controller is running to access status information and to pass control information. test registers registers that are intended to be used only for testing and diagnostic purposes. below is a list of the registers that fall into each of the first three categories. those registers that are not included amd p r e l i m i n a r y 106 AM79C970A in either of these lists can be assumed to be intended for diagnostic purposes. pci configuration registers the following is a list of those registers that would typi cally need to be programmed once during the initializa tion of the pcnet pci ii controller within a system: n pci i/o base address or memory mapped i/o base address register n pci expansion rom base address register n pci interrupt line register n pci latency timer register n pci status register n pci command register setup registers the following is a list of those registers that would typi cally need to be programmed once during the setup of the pcnet pci ii controller within a system. the control bits in each of these registers typically do not need to be modified once they have been written. however, there are no restrictions as to how many times these registers may actually be accessed. note that if the default power up values of any of these registers is acceptable to the application, then such registers need never be ac cessed at all. registers marked with ^" may be pro grammable through the eeprom read operation, and therefore do not necessarily need to be written to by the system initialization procedure or by the driver software. registers marked with *" will be initialized by the initiali zation block read operation. csr1 initialization block address[15:0] csr2 initialization block address[31:16] csr3 interrupt masks and deferral control csr4 test and features control csr5 extended control and interrupt csr8* logical address filter[15:0] csr9* logical address filter[31:16] csr10* logical address filter[47:32] csr11* logical address filter[63:48] csr12* physical address[15:0] csr13* physical address[31:16] csr14* physical address[47:32] csr15* mode csr24* base address of receive descriptor ring lower csr25* base address of receive descriptor ring upper csr30* base address of transmit descriptor ring lower csr31* base address of transmit descriptor ring upper csr47 polling interval csr76* receive descriptor ring length csr78* transmit descriptor ring length csr82 bus activity timer csr100 memory error timeout csr122 receiver packet alignment control bcr2^ miscellaneous configuration bcr4^ link status led bcr5^ led1 status bcr6^ led2 status bcr7^ led3 status bcr9^ full duplex control bcr18^ bus and burst control bcr20 software style running registers the following is a list of those registers that would typi cally need to be periodically read and perhaps written during the normal running operation of the pcnet pci ii controller within a system. each of these registers con tains control bits or status bits or both. rap register address port csr0 pcnet pci ii controller status csr4 test and features control csr5 extended control and interrupt csr112 missed frame count csr114 receive collision count pci status register pci configuration registers pci vendor id (offset 00h) the pci vendor id register is a 16 bit register that iden tifies the manufacturer of the pcnet pci ii controller. advanced micro devices, inc.'s (amd) vendor id is 1022h. note that this vendor id is not the same as the manufacturer id in csr88 and csr89. the vendor id is assigned by the pci special interest group. the pci vendor id register is located at offset 00h in the pci configuration space. it is read only. pci device id register (offset 02h) the pci device id register is a 16 bit register that uniquely identifies the pcnet pci ii controller within amd's product line. the pcnet pci ii controller device id is 2000h. note that this device id is not the same as the part number in csr88 and csr89. the device id is assigned by advanced micro devices, inc. p r e l i m i n a r y amd 107 AM79C970A the pci device id register is located at offset 02h in the pci configuration space. it is read only. pci command register (offset 04h) the pci command register is a 16 bit register used to control the gross functionality of the pcnet pci ii con troller. it controls the pcnet pci ii controller's ability to generate and respond to pci bus cycles. to logically disconnect the pcnet pci ii controller device from all pci bus cycles except configuration cycles, a value of zero should be written to this register. the pci command register is located at offset 04h in the pci configuration space. it is read and written by the host. bit name description 15-10 res reserved locations. read as zeros, write operations have no effect. 9 fbtben fast back to back enable. read as zero, write operations have no effect. the pcnet pci ii con troller will not generate fast back to back cycles. 8 serren serr enable. controls the as sertion of the serr pin. serr is disabled when serren is cleared. serr will be asserted on detection of an address parity error and if both serren and perren (bit 6 of this register) are set. serren is cleared by h_reset and is not effected by s_reset or by setting the stop bit. 7 adstep address/data stepping. read as zero, write operations have no effect. the pcnet-pci ii controller does not use address stepping. 6 perren parity error response enable. enables the parity error re- sponse functions. when perren is 0 and the pcnet- pci ii controller detects a parity error, it only sets the detected parity error bit in the pci status register. when perren is 1, the pcnet-pci ii controller as- serts perr on the detection of a data parity error. it also sets the dataperr bit (pci status register, bit 8), when the data parity error occurred during a master cycle. perren also en- ables reporting address parity er- rors through the serr pin and the serr bit in the pci status register. perren is cleared by h_reset and is not effected by s_reset or by setting the stop bit. 5 vgasnoop vga palette snoop. read as zero, write operations have no effect. 4 mwien memory write and invalidate cy- cle enable. read as zero, write operations have no effect. the pcnet-pci ii controller only gen- erates memory write cycles. 3 scycen special cycle enable. read as zero, write operations have no effect. the pcnet-pci ii controller ignores all special cycle operations. 2 bmen bus master enable. setting bmen enables the pcnet-pci ii controller to become a bus mas- ter on the pci bus. the host must set bmen before setting the init or strt bit in csr0 of the pcnet-pci ii controller. bmen is cleared by h_reset and is not effected by s_reset or by setting the stop bit. 1 memen memory space access enable. the pcnet-pci ii controller will ignore all memory accesses when memen is cleared. the host must set memen before the first memory access to the device. for memory mapped i/o, the host must program the pci mem- ory mapped i/o base address register with a valid memory ad- dress before setting memen. for accesses to the expansion rom, the host must program the pci expansion rom base address register at offset 30h with a valid memory address before setting memen. the pcnet-pci ii controller will only respond to accesses to the ex- pansion rom when both romen (pci expansion rom base address register, bit 0) and memen are set to one. since memen also enables the memory mapped access to the pcnet-pci ii controller i/o resources, the pci memory mapped i/o base address regis- ter must be programmed with an amd p r e l i m i n a r y 108 AM79C970A address so that the device does not claim cycles not intended for it. memen is cleared by h_reset and is not effected by s_reset or by setting the stop bit. 0 ioen i/o space access enable. the pcnet pci ii controller will ignore all i/o accesses when ioen is cleared. the host must set ioen before the first i/o access to the device. the pci i/o base address register must be programmed with a valid i/o ad dress before setting ioen. ioen is cleared by h_reset and is not effected by s_reset or by setting the stop bit. pci status register (offset 06h) the pci status register is a 16 bit register that contains status information for the pci bus related events. it is lo cated at offset 06h in the pci configuration space. bit name description 15 perr parity error. perr is set when the pcnet pci ii controller de tects a parity error. the pcnet pci ii controller sam ples the ad[31:0], c/ be [3:0] and the par lines for a parity error at the following times: in slave mode, during the address phase of any pci bus command. in slave mode, for all i/o, mem- ory and configuration write commands that select the pcnet-pci ii controller when data is transferred ( trdy and irdy are asserted). in master mode, during the data phase of all memory read commands. in master mode, during the data phase of the memory write com- mand, the pcnet-pci ii controller sets the perr bit if the target re- ports a data parity error by as- serting the perr signal. perr is not effected by the state of the parity error response en- able bit (pci command register, bit 6). perr is set by the pcnet-pci ii controller and cleared by writing a one. writing a zero has no effect. perr is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 14 serr signaled serr. serr is set when the pcnet-pci ii controller detects an address parity error, and both serren and perren (pci command register, bits 8 and 6) are set. serr is set by the pcnet-pci ii controller and cleared by writing a one. writing a zero has no effect. serr is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 13 rmabort received master abort. rmabort is set when the pcnet-pci ii controller termi- nates a master cycle with a mas- ter abort sequence. rmabort is set by the pcnet-pci ii controller and cleared by writing a one. writing a zero has no effect. rmabort is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 12 rtabort received target abort. rtabort is set when a target terminates a pcnet-pci ii con- troller master cycle with a target abort sequence. rtabort is set by the pcnet-pci ii controller and cleared by writing a one. writing a zero has no effect. rtabort is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 11 stabort send target abort. read as zero, write operations have no effect. the pcnet-pci ii con- troller will never terminate a slave access with a target abort sequence. stabort is read only. 10C9 devsel device select timing. devsel is set to 01b (medium), which means that the pcnet-pci ii controller will assert devsel two clock periods after frame is asserted. devsel is read only. 8 dataperr data parity error detected. dataperr is set when the pcnet-pci ii controller is the cur- rent bus master and it detects a p r e l i m i n a r y amd 109 AM79C970A data parity error and the parity error response enable bit (pci command register, bit 6) is set. during the data phase of all memory read commands, the pcnet pci ii controller checks for parity error by sampling the ad[31:0] and c/ be [3:0] and the par lines. during the data phase of all memory write commands, the pcnet-pci ii controller checks the perr input to detect whether the target has reported a parity error. dataperr is set by the pcnet- pci ii controller and cleared by writing a one. writing a zero has no effect. dataperr is cleared by h_reset and is not affected by s_reset or by set- ting the stop bit. 7 fbtbc fast back-to-back capable. read as one, write operations have no effect. the pcnet-pci ii controller is capable of accepting fast back-to-back transactions with the first transaction address- ing a different target. 6C0 res reserved locations. read as zero, write operations have no effect. pci revision id register (offset 08h) the pci revision id register is an 8-bit register that specifies the pcnet-pci ii controller revision number. the value of this register is 1xh, with the lower four bits being silicon-revision dependent. the pci revision id register is located at offset 08h in the pci configuration space. it is read only. pci programming interface register (offset 09h) the pci programming interface register is an 8-bit reg- ister that identifies the programming interface of pcnet-pci ii controller. pci does not define any specific register-level programming interfaces for network de- vices. the value of this register is 00h. the pci programming interface register is located at offset 09h in the pci configuration space. it is read only. pci sub-class register (offset 0ah) the pci sub-class register is an 8-bit register that iden- tifies specifically the function of the pcnet-pci ii control- ler. the value of this register is 00h which identifies the pcnet-pci ii controller device as an ethernet controller. the pci sub-class register is located at offset 0ah in the pci configuration space. it is read only. pci base-class register (offset 0bh) the pci base-class register is an 8-bit register that broadly classifies the function of the pcnet-pci ii controller. the value of this register is 02h which classifies the pcnet-pci ii controller device as a network controller. the pci base-class register is located at offset 0bh in the pci configuration space. it is read only. pci latency timer register (offset 0dh) the pci latency timer register is an 8-bit register that specifies the minimum guaranteed time the pcnet-pci ii controller will control the bus once it starts its bus mastership period. the time is measured in clock cycles. every time the pcnet-pci ii controller asserts frame at the beginning of a bus mastership period, it will copy the value of the pci latency timer register into a counter and start counting down. the counter will freeze at zero. when the system arbiter removes gnt while the counter is non-zero, the pcnet-pci ii con- troller will continue with its data transfers. it will only re- lease the bus when the counter has reached zero. the pci latency timer is only significant in burst trans- actions, where frame stays asserted until the last data phase. in a non-burst transaction, frame is only asserted during the address phase. the internal latency counter will be cleared and suspended while frame is deasserted. all 8 bits of the pci latency timer register are program- mable. the host should read the pcnet-pci ii controller pci min_gnt and pci max_lat registers to determine the latency requirements for the device and then initialize the latency timer register with an appropriate value. the pci latency timer register is located at offset 0dh in the pci configuration space. it is read and written by the host. the pci latency timer register is cleared by h_reset and is not effected by s_reset or by setting the stop bit. pci header type register (offset 0eh) the pci header type register is an 8-bit register that describes the format of the pci configuration space lo- cations 10h to 3ch and that identifies a device to be sin- gle or multi function. the pci header type register is located at address 0eh in the pci configuration space. it is read only. bit name description 7 funct single function/multi function de- vice. read as zero, write op- erations have no effect. the pcnet-pci ii controller is a single function device. amd p r e l i m i n a r y 110 AM79C970A 6-0 layout pci configuration space layout. read as zeros, write opera tions have no effect. the layout of the pci configuration space locations 10h to 3ch is as shown in the table at the beginning of this section. pci i/o base address register (offset 10h) the pci i/o base address register is a 32 bit register that determines the location of the pcnet pci ii control ler i/o resources in all of i/o space. it is located at offset 10h in the pci configuration space. 31-5 iobase i/o base address most signifi cant 27 bits. these bits are writ ten by the host to specify the location of the pcnet pci ii con troller i/o resources in all of i/o space. iobase must be written with a valid address before the pcnet pci ii controller slave i/o mode is turned on by setting the ioen bit (pci command regis ter, bit 0). when the pcnet pci ii controller is enabled for i/o mode (ioen is set), it monitors the pci bus for a valid i/o command. if the value on ad[31:5] during the address phase of the cycles matches the value of iobase, the pcnet pci ii controller will drive devsel indicating it will re- spond to the access. iobase is read and written by the host. iobase is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 4C2 iosize i/o size requirements. read as zeros, write operations have no effect. iosize indicates the size of the i/o space the pcnet-pci ii con- troller requires. when the host writes a value of ffff ffffh to the i/o base address register, it will read back a value of zero in bits 4C2. that indicates a pcnet-pci ii controller i/o space requirement of 32 bytes. 1 res reserved location. read as zero, write operations have no effect. 0 iospace i/o space indicator. read as one, write operations have no effect. indicating that this base address register describes an i/o base address. pci memory mapped i/o base address register (offset 14h) the pci memory mapped i/o base address register is a 32-bit register that determines the location of the pcnet-pci ii controller i/o resources in all of memory space. it is located at offset 14h in the pci configuration space. bit name description 31C5 membase memory mapped i/o base ad- dress most significant 27 bits. these bits are written by the host to specify the location of the pcnet-pci ii controller i/o re- sources in all of memory space. membase must be written with a valid address before the pcnet-pci ii controller slave memory mapped i/o mode is turned on by setting the memen bit (pci command register, bit 1). when the pcnet-pci ii controller is enabled for memory mapped i/o mode (memen is set), it monitors the pci bus for a valid memory command. if the value on ad[31:5] during the address phase of the cycles matches the value of membase, the pcnet-pci ii controller will drive devsel indicating it will re- spond to the access. membase is read and written by the host. membase is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 4 memsize memory mapped i/o size re- quirements. read as zeros, write operations have no effect. memsize indicates the size of the memory space the pcnet-pci ii controller requires. when the host writes a value of ffff ffffh to the memory mapped i/o base address regis- ter, it will read back a value of zero in bit 4. that indicates a pcnet-pci ii controller memory space requirement of 32 bytes. 3 prefetch prefetchable. read as zero, write operations have no effect. indicates that memory space controlled by this base address register is not prefetchable. data in the memory mapped i/o space cannot be prefetched. because one of i/o resources in this p r e l i m i n a r y amd 111 AM79C970A address space is a reset regis ter, the order of the read ac cesses is important. 2-1 type memory type indicator. read as zeros, write operations have no effect. indicates that this base address register is 32 bits wide and mapping can be done anywhere in the 32 bit memory space. 0 memspace memory space indicator. read as zero, write operations have no effect. indicates that this base address register describes a memory base address. pci expansion rom base address register (offset 30h) the pci expansion rom base address register is a 32 bit register that defines the base address, size and address alignment of an expansion rom. it is located at offset 30h in the pci configuration space. bit name description 31-16rombase expansion rom base address most significant 16 bits. these bits are written by the host to specify the location of the expan sion rom in all of memory space. rombase must be written with a valid address before the pcnet pci ii control ler expansion rom access is enabled by setting romen (pci expansion rom base address register, bit 0) and memen (pci command register, bit 1). since the 16 most significant bits of the base address areprogram mable, the host can map the expansion rom on any 64k boundary. when the pcnet pci ii controller is enabled for expansion rom access (romen and memen are set to one), it monitors the pci bus for a valid memory com mand. if the value on ad[31:2] during the address phase of the cycle falls between rombase and rombase + 64k - 4, the pcnet pci ii controller will drive devsel indicating it will re- spond to the access. rombase is read and written by the host. rombase is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 15C11romsize rom size. read as zeros, write operation have no effect. romsize indicates the maxi- mum size of the expansion rom the pcnet-pci ii controller can support. the host can determine the expansion rom size by writ- ing ffff f800h to the expansion rom base address register. it will read back a value of zero in bits 15C11, indicating an expan- sion rom size of 64k. note that romsize only speci- fies the maximum size of expan- sion rom the pcnet-pci ii controller supports. a smaller rom can be used, too. the actual size of the code in the ex- pansion rom is always deter- mined by reading the expansion rom header. 10C1 res reserved location. read as zeros, write operations have no effect. 0 romen expansion rom enable. written by the host to enable access to the expansion rom. the pcnet-pci ii controller will only respond to accesses to the ex- pansion rom when both romen and memen (pci com- mand register, bit 1) are set to one. romen is read and written by the host. romen is cleared by h_reset and is not effected by s_reset or by setting the stop bit. pci interrupt line register (offset 3ch) the pci interrupt line register is an 8-bit register that is used to communicate the routing of the interrupt. this register is written by the post software as it initializes the pcnet-pci ii controller in the system. the register is read by the network driver to determine the interrupt channel which the post software has assigned to the pcnet-pci ii controller. the pci interrupt line register is not modified by the pcnet-pci ii controller. it has no effect on the operation of the device. the pci interrupt line register is located at offset 3ch in the pci configuration space. it is read and written by the host. it is cleared by h_reset and is not affected s_reset or by setting the stop bit. pci interrupt pin register (offset 3dh) this pci interrupt pin register is an 8-bit register that in- dicates the interrupt pin that the pcnet-pci ii controller is using. the value for the pcnet-pci ii controller inter- rupt pin register is 01h, which corresponds to inta . the pci interrupt pin register is located at offset 3dh in the pci configuration space. it is read only. amd p r e l i m i n a r y 112 AM79C970A pci min_gnt register (offset 3eh) the pci min_gnt register is an 8 bit register that specifies the minimum length of a burst period that the pcnet pci ii controller needs to keep up with the net work activity. the length of the burst period is calculated assuming a clock rate of 33 mhz. the register value specifies the time in units of 1/4 ms. the pci min_gnt register is an alias of bcr22, bits 7-0. the default value for min_gnt is 06h, which corresponds to a minimum grant of 1.5 m s. one and a half m s is the time it takes the pcnet pci ii controller to read/write 64 bytes. (16 dword transfers in burst mode with one extra wait state per data phase inserted by the target.) note that the default is only a typical value. this calcula tion also does not take into account any descriptor ac cesses. the host should use the value in this register to deter mine the setting of the pci latency timer register. the pci min_gnt register is located at offset 3eh in the pci configuration space. it is read only. pci max_lat register (offset 3fh) the pci max_lat register is an 8 bit register that specifies the maximum arbitration latency the pcnet pci ii controller can sustain without causing problems to the network activity. the register value specifies the time in units of 1/4 microseconds. the max_lat register is an alias of bcr22, bits 15-8. the default value for max_lat is ffh, which corre sponds to a maximum latency of 63.75 m s. the actual maximum latency the pcnet pci ii controller can handle is 153.6 m s, which is also the value for the bus time out (see csr100). the host should use the value in this register to deter mine the setting of the pci latency timer register. the pci max_lat register is located at offset 3fh in the pci configuration space. it is read only. rap register the rap (register address pointer) register is used to gain access to csr and bcr registers on board the pcnet pci ii controller. the rap contains the address of a csr or bcr. as an example of rap use, consider a read access to csr4. in order to access this register, it is necessary to first load the value 0004h into the rap by performing a write access to the rap offset of 12h (12h when wio mode has been selected, 14h when dwio mode has been selected). then a second access is performed, this time to the rdp offset of 10h (for either wio or dwio mode). the rdp access is a read access, and since rap has just been loaded with the value of 0004h, the rdp read will yield the contents of csr4. a read of the bdp at this time (offset of 16h when wio mode has been selected, 1ch when dwio mode has been se lected) will yield the contents of bcr4, since the rap is used as the pointer into both bdp and rdp space. rap: register address port bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-8 res reserved locations. read and written as zeros. 7-0 rap register address port. the value of these 8 bits determines which csr or bcr will be accessed when an i/o access to the rdp or bdp port, respectively, is performed. a write access to undefined csr or bcr locations may cause unexpected reprogramming of the pcnet pci ii controller control registers. a read access will yield undefined values. read/write accessible always. rap is cleared by h_reset or s_reset and is unaffected by setting the stop bit. control and status registers the csr space is accessible by performing accesses to the rdp (register data port). the particular csr that is read or written during an rdp access will depend upon the current setting of the rap. rap serves as a pointer into the csr space. csr0: pcnet pci ii controller controller status register bit name description certain bits in csr0 indicate the cause of an interrupt. the regis ter is designed so that these indi cator bits are cleared by writing ones to those bit locations. this means that the software can read csr0 and write back the value just read to clear the interrupt condition. 31-16 res reserved locations. written as zeros and read as undefined. 15 err error is set by the oring of babl, cerr, miss, and merr. err remains set as long as any of the error flags are true. read accessible always. err is read only. write operations are ignored. 14 babl babble is a transmitter time out error. babl is set by the p r e l i m i n a r y amd 113 AM79C970A pcnet pci ii controller when the transmitter has been on the channel longer than the time required to send the maximum length frame. babl will be set if 1519 bytes or greater are transmitted. when babl is set, inta is as- serted if iena is one and the mask bit bablm (csr3, bit 14) is zero. babl assertion will set the err bit, regardless of the settings of iena and bablm. read/write accessible always. babl is cleared by the host by writing a one. writing a zero has no effect. babl is cleared by h_reset, s_reset or by set- ting the stop bit. 13 cerr collision error is set by the pcnet-pci ii controller when the device operates in half-duplex mode and the collision inputs to the aui or to the gpsi port failed to activate within 20 network bit times after the chip terminated transmission (sqe test). this feature is a transceiver test feature. cerr reporting is dis- abled when the aui or gpsi in- terface is active and the pcnet-pci ii controller operates in full-duplex mode. in 10base-t mode, for both half-duplex and full-duplex op- eration, cerr will be set after a transmission if the t-mau is in link fail state. cerr assertion will not result in an interrupt being generated. cerr assertion will set the err bit. read/write accessible always. cerr is cleared by the host by writing a one. writing a zero has no effect. cerr is cleared by h_reset, s_reset or by setting the stop bit. 12 miss missed frame is set by the pcnet-pci ii controller when it looses an incoming receive frame because a receive descrip- tor was not available. this bit is the only immediate indication that receive data has been lost since there is no current receive descriptor. the missed frame counter (csr112) also incre- ments each time a receive frame is missed. when miss is set, inta is as- serted if iena is one and the mask bit missm (csr3, bit 12) is zero. miss assertion will set the err bit, regardless of the settings of iena and missm. read/write accessible always. miss is cleared by the host by writing a one. writing a zero has no effect. miss is cleared by h_reset, s_reset or by set- ting the stop bit. 11 merr memory error is set by the pcnet-pci ii controller when it requests the use of the system interface bus by asserting req and gnt has not been asserted after a programmable length of time. the length of time in microseconds before merr is asserted will depend upon the setting of the bus timeout regis- ter (csr100). the default setting of csr100 will set merr after 153.6 m s of bus latency. when merr is set, inta is as- serted if iena is one and the mask bit merrm (csr3, bit 11) is zero. merr assertion will set the err bit, regardless of the settings of iena and merrm. read/write accessible always. merr is cleared by the host by writing a one. writing a zero has no effect. merr is cleared by h_reset, s_reset or by setting the stop bit. 10 rint receive interrupt is set by the pcnet-pci ii controller after the last descriptor of a receive frame has been updated by writing a zero to the own bit. rint may also be set when the first descrip- tor of a receive frame has been updated by writing a zero to the own bit if the lappen bit of csr3 has been set to one. when rint is set, inta is as- serted if iena is one and the mask bit rintm (csr3, bit 10) is zero. read/write accessible always. rint is cleared by the host by writing a one. writing a zero has no effect. rint is cleared by h_reset, s_reset or by setting the stop bit. 9 tint transmit interrupt is set by the pcnet-pci ii controller after the amd p r e l i m i n a r y 114 AM79C970A own bit in the last descriptor of a transmit frame has been cleared to indicate the frame has been sent or an error occurred in the transmission. when tint is set, inta is as- serted if iena is one and the mask bit tintm (csr3, bit 9) is zero. tint will not be set if tintokd (csr122, bit 2) is set to one and the transmission was successful. read/write accessible always. tint is cleared by the host by writing a one. writing a zero has no effect. tint is cleared by h_reset, s_reset or by set- ting the stop bit. 8 idon initialization done is set by the pcnet-pci ii controller after the initialization sequence has completed. when idon is set, the pcnet-pci ii controller has read the initialization block from memory. when idon is set, inta is as- serted if iena is one and the mask bit idonm (csr3, bit 8) is zero. read/write accessible always. idon is cleared by the host by writing a one. writing a zero has no effect. idon is cleared by h_reset, s_reset or by set- ting the stop bit. 7 intr interrupt flag indicates that one or more following interrupt caus- ing conditions has occurred: babl, exdint, idon, jab, merr, miss, mfco, mpint, rvcc, rint, sint, slpint, tint, txstrt or uint and the associated mask or enable bit is programmed to allow the event to cause an interrupt. if iena is set to one and intr is set, inta will be active. when intr is set by sint or slpint, inta will be ac- tive independent of the state of inea. read accessible always. intr is read only. intr is cleared by clearing all of the active individ- ual interrupt bits that have not been masked out. 6 iena interrupt enable allows inta to be active if the interrupt flag is set. if iena is cleared to zero, inta will be disabled regardless of the state of intr. read/write accessible always. iena is set by writing a one and cleared by writing a zero. iena is cleared by h_reset, s_reset or by setting the stop bit. 5 rxon receive on indicates that the re- ceive function is enabled. rxon is set to one if drx (csr15, bit 0) is cleared to zero after the start bit is set. if init and start are set together, rxon will not be set until after the in- itialization block has been read in. read accessible always. rxon is read only. rxon is cleared by h_reset, s_reset or by set- ting the stop bit. 4 txon transmit on indicates that the transmit function is enabled. txon is set to one if dtx (csr15, bit 1) is cleared to zero after the start bit is set. if init and start are set to- gether, txon will not be set until after the initialization block has been read in. read accessible always. txon is read only. txon is cleared by h_reset, s_reset or by set- ting the stop bit. 3 tdmd transmit demand, when set, causes the buffer management unit to access the transmit de- scriptor ring without waiting for the poll-time counter to elapse. if txon is not enabled, tdmd bit will be cleared and no transmit descriptor ring access will occur. if the dpoll bit in csr4 is set, automatic polling is disabled and tdmd can be used to start a transmission. read/write accessible always. tdmd is set by writing a one. writing a zero has no effect. tdmd will be cleared by the buffer management unit when it polls a transmit descriptor. tdmd is cleared by h_reset, s_reset or by setting the stop bit. 2 stop stop assertion disables the chip from all dma and network activ- ity. the chip remains inactive until either strt or init are set. if stop, strt and init are all set together, stop will override strt and init. p r e l i m i n a r y amd 115 AM79C970A read/write accessible always. stop is set by writing a one, by h_reset or s_reset. writing a zero has no effect. stop is cleared by setting either strt or init. 1 strt strt assertion enables the pcnet pci ii controller to send and receive frames and perform buffer management operations. setting strt clears the stop bit. if strt and init are set together, the pcnet pci ii controller initialization will be performed first. read/write accessible always. strt is set by writing a one. writing a zero has no effect. strt is cleared by h_reset, s_reset or by setting the stop bit. 0 init init assertion enables the pcnet pci ii controller to begin the initialization procedure which reads the initialization block from memory. setting init clears the stop bit. if strt and init are set together, the pcnet pci ii controller initialization will be per formed first. init is not cleared when the initialization sequence has completed. read/write accessible always. init is set by writing a one. writ ing a zero has no effect. init is cleared by h_reset, s_reset or by setting the stop bit. csr1: initialization block address 0 bit name description this register is aliased with csr16. 31-16 res reserved locations. written as zeros and read as undefined. 15-0 iadr[15:0] lower 16 bits of the address of the initialization block. bit loca tions 1 and 0 must both be zero to align the initialization block to a dword boundary. read/write accessible only when either the stop or the spnd bit is set. unaffected by h_reset or s_reset or by setting the stop bit. csr2: initialization block address 1 bit name description this register is aliased with csr17. 31-16 res reserved locations. written as zeros and read as undefined. 15-8iadr[31:24] if ssize32 (bcr20, bit 8) is cleared to zero, then the iadr[31:24] bits will be used to generate the upper 8 bits of all bus mastering addresses, as required for a 32 bit address bus. note that the 16 bit software structures will yield only 24 bits of address for pcnet pci ii control ler bus master accesses. the pcnet pci ii controller is de signed for 32 bit systems which require 32 bits of address. therefore, whenever ssize32 is cleared to zero, the iadr[31:24] bits will be ap pended to the 24 bit initialization address, to each 24 bit descrip tor base address and to each beginning 24 bit buffer address in order to form complete 32 bit addresses. the upper 8 bits that exist in the descriptor address registers and the buffer address registers which are stored on board the pcnet pci ii controller will be overwritten with the iadr[31:24] value, so that csr accesses to these registers will show the 32 bit address that in cludes the appended field. if ssize32 is set to one, then the iadr[31:24] bits will be used strictly as the upper 8 bits of the initialization block address. in this mode, software will pro vide 32 bit pointer values for all of the shared software struc tures i.e. descriptor bases and buffer addresses. read/write accessible only when either the stop or the spnd bit is set. unaffected by h_reset, s_reset or by set ting the stop bit. 7-0 iadr[23:16] bits 23 through 16 of the address of the initialization block. read/write accessible only when either the stop or the spnd bit is set. unaffected by h_reset, s_reset or by set ting the stop bit. amd p r e l i m i n a r y 116 AM79C970A csr3: interrupt masks and deferral control bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15 res reserved location. read and written as zero. 14 bablm babble mask. if bablm is set, the babl bit will be masked and unable to set the intr bit. read/write accessible always. bablm is cleared by h_reset or s_reset and is not affected by stop. 13 res reserved location. read and written as zero. 12 missm missed frame mask. if missm is set, the miss bit will be masked and unable to set the intr bit. read/write accessible always. missm is cleared by h_reset or s_reset and is not affected by stop. 11 merrm memory error mask. if merrm is set, the merr bit will be masked and unable to set the intr bit. read/write accessible always. merrm is cleared by h_reset or s_reset and is not affected by stop. 10 rintm receive interrupt mask. if rintm is set, the rint bit will be masked and unable to set the intr bit. read/write accessible always. rintm is cleared by h_reset or s_reset and is not affected by stop. 9 tintm transmit interrupt mask. if tintm is set, the tint bit will be masked and unable to set the intr bit. read/write accessible always. tintm is cleared by h_reset or s_reset and is not affected by stop. 8 idonm initialization done mask. if idonm is set, the idon bit will be masked and unable to set the intr bit. read/write accessible always. idonm is cleared by h_reset or s_reset and is not affected by stop. 7 res reserved location. read and written as zeros. 6 dxsuflo disable transmit stop on under flow error. when dxsuflo is cleared to zero, the transmitter is turned off when an uflo error occurs (csr0, txon = 0). when dxsuflo is set to one, the pcnet pci ii controller gracefully recovers from an uflo error. it scans the transmit descriptor ring until it finds the start of a new frame and starts a new transmission. read/write accessible always. dxsuflo is cleared by h_reset or s_reset and is not affected by stop. 5 lappen look ahead packet processing enable. when set to one, the lappen bit will cause the pcnet pci ii controller to gener ate an interrupt following the de scriptor write operation to the first buffer of a receive frame. this interrupt will be generated in ad dition to the interrupt that is gen erated following the descriptor write operation to the last buffer of a receive packet. the interrupt will be signaled through the rint bit of csr0. setting lappen to one also en ables the pcnet pci ii controller to read the stp bit of receive de scriptors. the pcnet pci ii con troller will use the stp information to determine where it should begin writing a receive packet's data. note that while in this mode, the pcnet pci ii con troller can write intermediate packet data to buffers whose descriptors do not contain stp bits set to one. following the write to the last descriptor used by a packet, the pcnet pci ii controller will scan through the next descriptor entries to locate the next stp bit that is set to one. the pcnet pci ii controller will begin writing the next pack et's data to the buffer pointed to by that descriptor. note that because several de scriptors may be allocated by the host for each packet, and not all messages may need all of the de scriptors that are allocated between descriptors that have stp set to one, then some de scriptors/buffers may be skipped p r e l i m i n a r y amd 117 AM79C970A in the ring. while performing the search for the next stp bit that is set to one, the pcnet pci ii controller will advance through the receive descriptor ring re gardless of the state of owner ship bits. if any of the entries that are examined during this search indicate pcnet pci ii controller ownership of the descriptor but also have stp cleared to zero, the pcnet pci ii controller will clear the own bit to zero in these entries. if a scanned entry indicates host ownership with stp cleared to zero, the pcnet pci ii controller will not al ter the entry, but will advance to the next entry. when the stp bit is set to one, but the descriptor that contains this setting is not owned by the pcnet pci ii controller, then the pcnet pci ii controller will stop advancing through the ring en tries and begin periodic polling of this entry. when the stp bit is set to one, and the descriptor that contains this setting is owned by the pcnet pci ii controller, then the pcnet pci ii controller will stop advancing through the ring entries, store the descriptor infor mation that it has just read, and wait for the next receive to arrive. this behavior allows the host software to pre assign buffer space in such a manner that the header portion of a receive packet will always be written to a particular memory area, and the data portion of a receive packet will always be written to a sepa rate memory area. the interrupt is generated when the header bytes have been written to the header memory area. read/write accessible always. lappen bit is cleared by h_reset or s_reset and is not affected by stop. see appendix d for more infor mation on the look ahead packet processing concept. 4 dxmt2pd disable transmit two part de ferral (see the section medium allocation" for more details). if dxmt2pd is set, transmit two part deferral will be disabled. read/write accessible always. dxmt2pd is cleared by h_reset or s_reset and is not affected by stop. 3 emba enable modified back off algo rithm (see the section collision handling" for more details). if emba is set, a modified back off algorithm is implemented. read/write accessible always. emba is cleared by h_reset or s_reset and is not affected by stop. 2 bswp byte swap. this bit is used to choose between big and little endian modes of operation. when bswp is set to one, big endian mode is selected. when bswp is cleared to zero, little endian mode is selected. when big endian mode is se lected, the pcnet pci ii control ler will swap the order of bytes on the ad bus during a data phase on accesses to the fifos only: ad[31:24] is byte 0, ad[23:16] is byte 1, ad[15:8] is byte 2 and ad[7:0] is byte 3. when little endian mode is se lected, the order of bytes on the ad bus during a data phase is: ad[31:24] is byte 3, ad[23:16] is byte 2, ad[15:8] is byte 1 and ad[7:0] is byte 0. byte swap only affects data transfers that involve the fifos. initialization block transfers, de scriptor transfers, rdp, rap, bdp and pci configuration space accesses, address prom transfers, and expansion rom accesses are not affected by the setting of the bswp bit. note that the byte ordering of the pci bus is defined to be little endian. bswp should not be set to one when the pcnet pci ii controller is used in a pci bus application. read/write accessible always. bswp is cleared by h_reset or s_reset and is not affected by stop. 1 res reserved location. the default value of this bit is a zero. writ ing a one to this bit has no effect on device function. if a one is written to this bit, then a one will be read back. existing drivers may write a one to this bit for compatibility, but new drivers should write a zero to this bit amd p r e l i m i n a r y 118 AM79C970A and should treat the read value as undefined. 0 res reserved location. the default value of this bit is a zero. writ ing a one to this bit has no effect on device function. if a one is written to this bit, then a one will be read back. existing drivers may write a one to this bit for compatibility, but new drivers should write a zero to this bit and should treat the read value as undefined. csr4: test and features control bit name description certain bits in csr4 indicate the cause of an interrupt. the regis ter is designed so that these indicator bits are cleared by writ ing ones to those bit locations. this means that the software can read csr4 and write back the value just read to clear the interrupt condition. 31-16 res reserved locations. written as zeros and read as undefined. 15 en124 enable csr124 access. setting en124 to one allows the user to write to bits in csr124 which enable the gpsi interface (gpsien, bit 4) and runt packet accept mode (rpa, bit 3). once these bits are accessed en124 must be cleared back to zero. read/write accessible always. en124 is cleared by h_reset or s_reset and is unaffected by setting the stop bit. in order to set en124, it must be written with a one during the first write access to csr4 after h_reset or s_reset. once a zero is written to this bit position, en124 cannot be set until after the pcnet pci ii controller is reset by h_reset or s_reset. 14 dmaplus when dmaplus is set to one, the dma burst transfer counter in csr80 is disabled. if dmaplus is cleared to zero, the counter is enabled. dmaplus should be set to one when the pcnet pci ii controller is used in a pci bus application. read/write accessible always. dmaplus is cleared by h_reset or s_reset and is unaffected by setting the stop bit. 13 timer enable bus activity timer. if timer is set to one, the bus ac tivity timer (csr82) is enabled. if timer is cleared, the bus ac tivity timer is disabled. timer should stay at its default value of zero when the pcnet pci ii controller is used in a pci bus application. read/write accessible always. timer is cleared by h_reset or s_reset and is unaffected by setting the stop bit. 12 dpoll disable transmit polling. if dpoll is set, the buffer man agement unit will disable trans mit polling. if dpoll is cleared, automatic transmit polling is en abled. if dpoll is set, the tdmd bit in csr0 must be set in order to initiate a manual poll of a transmit descriptor. transmit de scriptor polling will not take place if txon is cleared. read/write accessible always. dpoll is cleared by h_reset or s_reset and is unaffected by setting the stop bit. 11 apad_xmt auto pad transmit. when set, apad_xmt enables the auto matic padding feature. transmit frames will be padded to extend them to 64 bytes including fcs. the fcs is calculated for the en tire frame including pad, and appended after the pad. apad_xmt will override the pro gramming of the dxmtfcs bit (csr15, bit 3) and of the add_fcs/no_fcs bit (tmd1, bit 29). read/write accessible always. apad_xmt is cleared by h_reset or s_reset and is unaffected by setting the stop bit. 10 astrp_rcv auto strip receive. when set, astrp_rcv enables the auto matic pad stripping feature. the pad and fcs fields will be stripped from receive frames and not placed in the fifo. read/write accessible always. astrp_rcv is cleared by h_reset or s_reset and is unaffected by setting the stop bit. p r e l i m i n a r y amd 119 AM79C970A 9 mfco missed frame counter overflow is set by the pcnet pci ii controller when the missed frame counter (csr112) wraps around. when mfco is set, inta is as- serted if iena is one and the mask bit mfcom is zero. read/write accessible always. mfco is cleared by the host by writing a one. writing a zero has no effect. mfco is cleared by h_reset, s_reset or by setting the stop bit. when the value 01h has been programmed into the swstyle register (bcr20, bits 7C0) for ilacc (am79c900) compatibil- ity, then this bit has no meaning and pcnet-pci ii controller will never set the value of this bit to one. 8 mfcom missed frame counter overflow mask. if mfcom is set, the mfco bit will be masked and un- able to set the intr bit. read/write accessible always. mfcom is set to one by h_reset or s_reset and is unaffected by setting the stop bit. when the value 01h has been programmed into the swstyle register (bcr20, bits 7C0) for ilacc (am79c900) compatibility, then this bit has no meaning and pcnet-pci ii con- troller will clear the value of this bit to zero. 7 uintcmd user interrupt command. uintcmd can be used by the host to generate an interrupt un- related to any network activity. when uintcmd is set, inta is asserted if iena is set to one. uintcmd will be cleared internally after the pcnet-pci ii controller has set uint to one. read/write accessible always. uintcmd is cleared by h_reset or s_reset or by setting the stop bit. 6 uint user interrupt. uint is set by the pcnet-pci ii controller after the host has issued a user interrupt command by setting uintcmd (csr4, bit 7) to one. read/write accessible always. uint is cleared by the host by writing a one. writing a zero has no effect. uint is cleared by h_reset or s_reset or by setting the stop bit. 5 rcvcco receive collision counter over- flow is set by the pcnet-pci ii controller when the receive collision counter (csr114) wraps around. when rcvcco is set, inta is asserted if iena is one and the mask bit rcvccom is zero. read/write accessible always. rcvcco is cleared by the host by writing a one. writing a zero has no effect. rcvcco is cleared by h_reset, s_reset or by setting the stop bit. when the value 01h has been programmed into the swstyle register (bcr20, bits 7C0) for ilacc (am79c900) compatibil- ity, then this bit has no meaning and pcnet-pci ii controller will never set the value of this bit to one. 4 rcvccom receive collision counter over- flow mask. if rcvccom is set, the rcvcco bit will be masked and unable to set the intr bit. read/write accessible always. rcvccom is set to one by h_reset or s_reset and is unaffected by setting the stop bit. when the value 01h has been programmed into the swstyle register (bcr20, bits 7C0) for ilacc (am79c900) compatibil- ity, then this bit has no meaning and pcnet-pci ii controller will clear the value of this bit to zero. 3 txstrt transmit start status is set by the pcnet-pci ii controller whenever it begins transmission of a frame. when txstrt is set, inta is as- serted if iena is one and the mask bit txstrtm is zero. read/write accessible always. txstrt is cleared by the host by writing a one. writing a zero has no effect. txstrt is cleared by h_reset, s_reset or by setting the stop bit. 2 txstrtm transmit start mask. if txstrtm is set, the txstrt bit will be masked and unable to set the intr bit. amd p r e l i m i n a r y 120 AM79C970A read/write accessible always. txstrtm is set to one by h_reset or s_reset and is unaffected by setting the stop bit. 1 jab jabber error is set by the pcnet pci ii controller when the t mau exceeds the allowed transmis sion time limit. jabber can only be asserted in 10base t mode. when jab is set, inta is as- serted if iena is one and the mask bit jabm is zero. read/write accessible always. jab is cleared by the host by writ- ing a one. writing a zero has no effect. jab is cleared by h_reset, s_reset or by set- ting the stop bit. when the value 01h has been programmed into the swstyle register (bcr20, bits 7C0) for ilacc (am79c900) compatibil- ity, then this bit has no meaning and pcnet-pci ii controller will never set the value of this bit to one. 0 jabm jabber error mask. if jabm is set, the jab bit will be masked and unable to set the intr bit. read/write accessible always. jabm is set to one by h_reset or s_reset and is unaffected by setting the stop bit. when the value 01h has been programmed into the swstyle register (bcr20, bits 7C0) for ilacc (am79c900) compatibil- ity, then this bit has no meaning and pcnet-pci ii controller will clear the value of this bit to zero. csr5: extended control and interrupt bit name description certain bits in csr5 indicate the cause of an interrupt. the regis- ter is designed so that these indi- cator bits are cleared by writing ones to those bit locations. this means that the software can read csr5 and write back the value just read to clear the interrupt condition. 31C16 res reserved locations. written as zeros and read as undefined. 15 tokintd transmit ok interrupt disable. if tokintd is set to one, the tint bit in csr0 will not be set when a transmission was suc- cessful. only a transmit error will set the tint bit. tokintd has no effect when ltinten (csr5, bit 14) is set to one. a transmit descriptor with ltint set to one will always cause tint to be set to one, in- dependent of the success of the transmission. read/write accessible always. tokintd is cleared by h_reset or s_reset and is unaffected by setting the stop bit. 14 ltinten last transmit interrupt enable. when set to one, the ltinten bit will cause the pcnet-pci ii controller to read bit 28 of tmd1 as ltint. the setting ltint will determine if tint will be set at the end of the transmission. read/write accessible always. ltinten is cleared by h_reset or s_reset and is unaffected by setting the stop bit. 13C12 res reserved locations. written as zeros and read as undefined. 11 sint system interrupt is set by the pcnet-pci ii controller when it detects a system error during a bus master transfer on the pci bus. system errors are data par- ity error, master abort or a target abort. the setting of sint due to a data parity error is not depend- ent on the setting of perren (pci command register, bit 6). when sint is set, inta is as- serted if the enable bit sinte is one. note that the assertion of an interrupt due to sint is not de- pendent on the state of the inea bit, since inea is cleared by the stop reset generated by the system error. read/write accessible always. sint is cleared by the host by writing a one. writing a zero has no effect. the state of sint is not affected by clearing any of the pci status register bits that get set when a data parity error (dataperr, bit 8), master abort (rmabort, bit 13) or target p r e l i m i n a r y amd 121 AM79C970A abort (rtabort, bit 12) occurs. sint is cleared by h_reset or s_reset and is not affected by setting the stop bit. 10 sinte system interrupt enable. if sinte is set, the sint bit will be able to set the intr bit. read/write accessible always. sinte is cleared to zero by h_reset or s_reset and is not affected by setting the stop bit. 9 slpint sleep interrupt is set by the pcnet pci ii controller when it comes out of sleep mode. when slpint is set, inta is as- serted if the enable bit slpinte is one. note that the assertion of an interrupt due to slpint is not dependent on the state of the inea bit, since inea is cleared by s_reset when entering the sleep mode. read/write accessible always. slpint is cleared by the host by writing a one. writing a zero has no effect. slpint is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 8 slpinte sleep interrupt enable. if slpinte is set, the slpint bit will be able to set the intr bit. read/write accessible always. slpinte is cleared to zero by h_reset and is not affected by s_reset or by setting the stop bit. 7 exdint excessive deferral interrupt is set by the pcnet-pci ii controller when the transmitter has experi- enced excessive deferral on a transmit frame, where excessive deferral is defined in iso 8802-3 (ieee/ansi 802.3). when exdint is set, inta is as- serted if the enable bit exdinte is one. read/write accessible always. exdint is cleared by the host by writing a one. writing a zero has no effect. exdint is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 6 exdinte excessive deferral interrupt en- able. if exdinte is set, the ex- dint bit will be able to set the intr bit. read/write accessible always. exdinte is cleared to zero by h_reset and is not affected by s_reset or by setting the stop bit. 5 mpplba magic packet physical logical broadcast accept. if mpplba is cleared to zero, the pcnet-pci ii controller will only detect a magic packet if the destination address of the packet matches the content of the physical ad- dress register (padr). if mpplba is set to one, the desti- nation address of the magic packet can be unicast, multicast or broadcast. note that the set- ting of mpplba only effects the address detection of the magic packet. the magic packet data sequence must be in all cases the same, i.e., a 16-times repeti- tion of the the physical address (padr[47:0]). read/write accessible always. mpplba is cleared to zero by h_reset or s_reset and is not affected by setting the stop bit. 4 mpint magic packet interrupt is set by the pcnet-pci ii controller when the device is in magic packet mode and it receives a magic packet. when mpint is set, inta is as- serted if iena (csr0, bit 6) and the enable bit mpinte are set to one. read/write accessible always. mpint is cleared by the host by writing a one. writing a zero has no effect. mpint is cleared by h_reset, s_reset or by setting the stop bit. 3 mpinte magic packet interrupt enable. if mpinte is set, the mpint bit will be able to set the intr bit. read/write accessible always. mpinte is cleared to zero by h_reset or s_reset and is not affected by setting the stop bit. 2 mpen magic packet enable. mpen al- lows activation of the magic packet mode by software. the pcnet-pci ii controller will enter the magic packet mode when both mpen and mpmode are set to one. amd p r e l i m i n a r y 122 AM79C970A read/write accessible always. mpen is cleared to zero by h_reset or s_reset and is not affected by setting the stop bit. 1 mpmode magic packet mode. setting mpmode to one will redefine the sleep pin to be a magic packet enable pin. the pcnet-pci ii controller will enter the magic packet mode when mpmode is set to one and either sleep is asserted or mpen is set to one. read/write accessible always. mpmode is cleared to zero by h_reset or s_reset and is not affected by setting the stop bit. 0 spnd suspend. setting spnd to one will cause the pcnet-pci ii con- troller to start entering the sus- pend mode. the host must poll spnd until it reads back one to determine that the pcnet-pci ii controller has entered the sus- pend mode. setting spnd to zero will get the pcnet-pci ii controller out of suspend mode. spnd can only be set to one if stop (csr0, bit 2) is cleared to zero. h_reset, s_reset or setting the stop bit will get the pcnet-pci ii controller out of suspend mode. when the host requests the pcnet-pci ii controller to enter the suspend mode, the device first finishes all on-going transmit activity and updates the corre- sponding transmit descriptor en- tries. it then finishes all on-going receive activity and updates the corresponding receive descriptor entries. it then sets the read-ver- sion of spnd to one and enters the suspend mode. in suspend mode, all of the csr and bcr registers are accessible. as long as the pcnet-pci ii controller is not re- set while in suspend mode (by h_reset, s_reset or by set- ting the stop bit), no re-initiali- zation of the device is required after the device comes out of suspend mode. the pcnet-pci ii controller will continue at the transmit and receive descriptor ring locations where it had left off. read/write accessible always. spnd is cleared by h_reset, s_reset or by setting the stop bit. csr6: rx/tx descriptor table length bit name description 31C16 res reserved locations. written as zeros and read as undefined. 15C12 tlen contains a copy of the transmit encoded ring length (tlen) field read from the initialization block during pcnet-pci ii controller in- itialization. this field is written during the pcnet-pci ii controller initialization routine. read accessible only when either the stop or the spnd bit is set. write operations have no effect and should not be per- formed. tlen is only defined after initialization. these bits are unaffected by h_reset, s_reset or by setting the stop bit. 11C8 rlen contains a copy of the receive encoded ring length (rlen) read from the initialization block during pcnet-pci ii controller initialization. this field is written during the pcnet-pci ii controller initialization routine. read accessible only when either the stop or the spnd bit is set. write operations have no effect and should not be per- formed. rlen is only defined af- ter initialization. these bits are unaffected by h_reset, s_reset or by setting the stop bit. 7C0 res reserved locations. read as zeros. write operations are ignored. csr8: logical address filter 0 bit name description 31C16 res reserved locations. written as zeros and read as undefined. 15C0ladrf[15:0] logical address filter, ladrf[15:0]. the content of this register is undefined until loaded from the initialization block after the init bit in csr0 has been set or a direct register write has been performed on this register. read/write accessible only when either the stop or the spnd bit is set. these bits p r e l i m i n a r y amd 123 AM79C970A are unaffected by h_reset, s_reset or by setting the stop bit. csr9: logical address filter 1 bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0ladrf[31:16] logical address filter, ladrf[31:16]. the content of this register is undefined until loaded from the initialization block after the init bit in csr0 has been set or a direct register write has been performed on this register. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr10: logical address filter 2 bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0ladrf[47:32] logical address filter, ladrf[47:32]. the content of this register is undefined until loaded from the initialization block after the init bit in csr0 has been set or a direct register write has been performed on this register. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr11: logical address filter 3 bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0ladrf[63:48] logical address filter, ladrf[63:48]. the content of this register is undefined until loaded from the initialization block after the init bit in csr0 has been set or a direct register write has been performed on this register. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr12: physical address register 0 bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0padr[15:0] physical address register, padr[15:0]. the content of this register is undefined until loaded from the initialization block after the init bit in csr0 has been set or a direct register write has been performed on this register. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr13: physical address register 1 bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0padr[31:16] physical address register, padr[31:16]. the content of this register is undefined until loaded from the initialization block after the init bit in csr0 has been set or a direct register write has been performed on this register. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr14: physical address register 2 bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0padr[47:32] physical address register, padr[47:32]. the content of this register is undefined until loaded from the initialization block after the init bit in csr0 has been set or a direct register write has been performed on this register. amd p r e l i m i n a r y 124 AM79C970A read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr15: mode bit name description this register's fields are loaded during the pcnet pci ii controller initialization routine with the cor responding initialization block values. the host can also write directly to this register. 31-16 res reserved locations. written as zeros and read as undefined. 15 prom promiscuous mode. when prom is set to one, all incoming receive frames are accepted. read/write accessible only when either the stop or the spnd bit is set. 14 drcvbc disable receive broadcast. when set, this bit disables the pcnet pci ii controller from receiving broadcast messages. drcvbc has no effect when prom is set to one. read/write accessible only when either the stop or the spnd bit is set. drcvbc is cleared by h_reset or s_reset and not affected by stop. 13 drcvpa disable receive physical ad dress. when set, the physical ad dress detection (station or node id) of the pcnet pci ii controller will be disabled. frames ad dressed to the node's individual physical address will not be rec ognized. drcvpa has no effect when prom is set to one. read/write accessible only when either the stop or the spnd bit is set. 12 dlnktst disable link status. when dlnktst is set to one, moni toring of link pulses is disabled. when dlnktst is cleared to zero, monitoring of link pulses is enabled. this bit only has meaning when the 10base t network interface is selected. read/write accessible only when either the stop or the spnd bit is set. 11 dapc disable automatic polarity cor rection. when dapc is set to one, the 10base t receive po larity reversal algorithm is dis abled. when dapc is cleared to zero, the polarity reversal algo rithm is enabled. this bit only has meaning when the 10base t network interface is selected. read/write accessible only when either the stop or the spnd bit is set. 10 mendecl mendec loopback mode. see the description of the loop bit in csr15. read/write accessible only when either the stop or the spnd bit is set. 9 lrt low receive threshold (t mau mode only) tsel transmit mode select (aui mode only) lrt low receive threshold. when lrt is set to one, the internal twisted pair receive thresholds are reduced by 4.5 db below the standard 10base t value (approximately 3/5) and the unsquelch threshold for the rxd circuit will be 180 mv- 312 mv peak. table 23. network port configuration asel link status portsel[1:0] (bcr2[1]) (of 10base t) network port 0x 1 fail aui 0x 1 pass 10base t 00 0 x aui 01 0 x 10base t 10 x x gpsi 11 x x reserved p r e l i m i n a r y amd 125 AM79C970A when lrt is cleared to zero, the unsquelch threshold for the rxd circuit will be the standard 10base t value of 300 mv- 520 mv peak. in either case, the rxd circuit post squelch threshold will be one half of the unsquelch threshold. this bit only has meaning when the 10base t network interface is selected. read/write accessible only when either the stop or the spnd bit is set. cleared by h_reset or s_reset and is unaffected by setting the stop bit. tsel transmit mode select. tsel controls the levels at which the aui drivers rest when the aui transmit port is idle. when tsel is cleared to zero, do+ and do- yield zero differential to op erate transformer coupled loads (ethernet 2 and 802.3). when tsel is set to one, the do+ idles at a higher value with re spect to do-, yielding a logical high state (ethernet 1). this bit only has meaning when the aui network interface is selected. read/write accessible only when either the stop or the spnd bit is set. cleared by h_reset or s_reset. 8-7portsel[1:0] port select bits allow for software controlled selection of the net work medium. gpsien (csr124, bit 4) must be set to one in addition to pro gramming the portsel bits in order to select the gpsi port as the active network port. portsel settings of aui and 10base t are ignored when the asel bit of bcr2 (bit 1) has been set to one. read/write accessible only when either the stop or the spnd bit is set. cleared by h_reset or s_reset and is unaffected by setting the stop bit. 6 intl internal loopback. see the de scription of loop (csr15, bit 2). read/write accessible only when either the stop or the spnd bit is set. 5 drty disable retry. when drty is set to one, pcnet pci ii control ler will attempt only one transmission. in this mode, the device will not protect the first 64 bytes of frame data in the trans mit fifo from being overwritten, because automatic re transmis sion will not be necessary. when drty is cleared to zero, the pcnet pci ii controller will at tempt 16 transmissions before signaling a retry error. read/write accessible only when either the stop or the spnd bit is set. 4 fcoll force collision. this bit allows the collision logic to be tested. the pcnet pci ii controller must be in internal loopback for fcoll to be valid. if fcoll is set to one, a collision will be forced during loopback transmis sion attempts, which will result in a retry error. if fcoll is cleared to zero, the force collision logic will be disabled. fcoll is defined after the initialization block is read. table 24. loopback configuration loop intl mendecl loopback mode 0 x x non loopback 1 0 x external loopback 1 1 0 internal loopback include mendec 1 1 1 internal loopback exclude mendec amd p r e l i m i n a r y 126 AM79C970A read/write accessible only when either the stop or the spnd bit is set. 3 dxmtfcs disable transmit crc (fcs). when dxmtfcs is cleared to zero, the transmitter will generate and append an fcs to the transmitted frame. when dxmtfcs is set to one, no fcs is generated or sent with the transmitted frame. dxmtfcs is overridden when add_fcs is set in tmd1. if dxmtfcs is set and add_fcs is clear for a particular frame, no fcs will be generated. the value of add_fcs is valid only when stp is set in tmd1. if add_fcs is set for a particular frame, the state of dxmtfcs is ignored and a fcs will be ap pended on that frame by the transmit circuitry. see also the add_fcs bit in tmd1. this bit is called dtcr in the c lance (am79c90). read/write accessible only when either the stop or the spnd bit is set. 2 loop loopback enable allows pcnet pci ii controller to oper ate in full duplex mode for test purposes. the setting of the full duplex control bits in bcr9 have no effect when the device operates in loopback mode. when loop is set to one, loopback is enabled. in combina tion with intl and mendecl, various loopback modes are defined in the loopback configuration table. read/write accessible only when either the stop or the spnd bit is set. loop is cleared by h_reset or s_reset and is unaffected by setting the stop bit. 1 dtx disable transmit. when dtx is set to one, the pcnet pci ii con troller will not access the transmit descriptor ring and therefore no transmissions are attempted. when dtx is cleared to zero, txon (csr0, bit 4) is set to one after strt (csr0, bit 1) has been set to one. read/write accessible only when either the stop or the spnd bit is set. 0 drx disable receiver. when drx is set to one, the pcnet pci ii con troller will not access the receive descriptor ring and therefore all receive frame data are ignored. when drx is cleared to zero, rxon (csr0, bit 5) is set to one after strt (csr0, bit 1) has been set to one. read/write accessible only when either the stop or the spnd bit is set. csr16: initialization block address lower bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 iadrl this register is an alias of csr1. read/write accessible only when either the stop or the spnd bit is set. csr17: initialization block address upper bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 iadrh this register is an alias of csr2. read/write accessible only when either the stop or the spnd bit is set. csr18: current receive buffer address lower bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 crbal contains the lower 16 bits of the current receive buffer address at which the pcnet pci ii controller will store incoming frame data. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr19: current receive buffer address upper bit name description 31-16 res reserved locations. written as zeros and read as undefined. p r e l i m i n a r y amd 127 AM79C970A 15-0 crbau contains the upper 16 bits of the current receive buffer address at which the pcnet pci ii controller will store incoming frame data. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr20: current transmit buffer address lower bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 cxbal contains the lower 16 bits of the current transmit buffer address from which the pcnet pci ii con troller is transmitting. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr21: current transmit buffer address upper bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 cxbau contains the upper 16 bits of the current transmit buffer address from which the pcnet pci ii con troller is transmitting. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr22: next receive buffer address lower bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 nrbal contains the lower 16 bits of the next receive buffer address to which the pcnet pci ii controller will store incoming frame data. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr23: next receive buffer address upper bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 nrbau contains the upper 16 bits of the next receive buffer address to which the pcnet pci ii controller will store incoming frame data. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr24: base address of receive descriptor ring lower bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 badrl contains the lower 16 bits of the base address of the receive descriptor ring. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr25: base address of receive descriptor ring upper bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 badru contains the upper 16 bits of the base address of the receive descriptor ring. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, amd p r e l i m i n a r y 128 AM79C970A s_reset or by setting the stop bit. csr26: next receive descriptor address lower bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 nrdal contains the lower 16 bits of the next receive descriptor address pointer. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr27: next receive descriptor address upper bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 nrdau contains the upper 16 bits of the next receive descriptor address pointer. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr28: current receive descriptor address lower bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 crdal contains the lower 16 bits of the current receive descriptor address pointer. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr29: current receive descriptor address upper bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 crdau contains the upper 16 bits of the current receive descriptor address pointer. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr30: base address of transmit descriptor ring lower bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 badxl contains the lower 16 bits of the base address of the transmit descriptor ring. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr31: base address of transmit descriptor ring upper bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 badxu contains the upper 16 bits of the base address of the transmit descriptor ring. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr32: next transmit descriptor address lower bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 nxdal contains the lower 16 bits of the next transmit descriptor address pointer. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. p r e l i m i n a r y amd 129 AM79C970A csr33: next transmit descriptor address upper bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 nxdau contains the upper 16 bits of the next transmit descriptor address pointer. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr34: current transmit descriptor address lower bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 cxdal contains the lower 16 bits of the current transmit descriptor address pointer. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr35: current transmit descriptor address upper bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 cxdau contains the upper 16 bits of the current transmit descriptor ad dress pointer. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr36: next next receive descriptor address lower bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 nnrdal contains the lower 16 bits of the next next receive descriptor address pointer. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr37: next next receive descriptor address upper bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 nnrdau contains the upper 16 bits of the next next receive descriptor address pointer. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr38: next next transmit descriptor address lower bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 nnxdal contains the lower 16 bits of the next next transmit descriptor address pointer. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr39: next next transmit descriptor address upper bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 nnxdau contains the upper 16 bits of the next next transmit descriptor address pointer. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. amd p r e l i m i n a r y 130 AM79C970A csr40: current receive byte count bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-12 res reserved locations. read and written as zeros. 11-0 crbc current receive byte count. this field is a copy of the bcnt field of rmd1 of the current receive descriptor. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr41: current receive status bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 crst current receive status. this field is a copy of bits 31-16 of rmd1 of the current receive descriptor. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr42: current transmit byte count bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-12 res reserved locations. read and written as zeros. 11-0 cxbc current transmit byte count. this field is a copy of the bcnt field of tmd1 of the current transmit descriptor. 15-0 cxst current transmit status. this field is a copy of bits 31-16 of tmd1 of the current transmit descriptor. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr44: next receive byte count bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-12 res reserved locations. read and written as zeros. 11-0 nrbc next receive byte count. this field is a copy of the bcnt field of rmd1 of the next receive descriptor. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr45: next receive status bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 nrst next receive status. this field is a copy of bits 31-16 of rmd1 of the next receive descriptor. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr46: poll time counter bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 poll poll time counter. this counter is incremented by the pcnet pci ii controller microcode and is used to trigger the descriptor ring polling operation of the pcnet pci ii controller. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. p r e l i m i n a r y amd 131 AM79C970A csr47: polling interval bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 pollint polling interval. this register contains the time that the pcnet pci ii controller will wait between successive polling op erations. the pollint value is expressed as the two's comple ment of the desired interval, where each bit of pollint rep resents one clock period. pollint[3:0] are ignored. the sign of the two's complement pollint value is implied to be a one, so pollint[15] does not represent the sign bit, but is the msb of the number. the default value of this register is 0000h. this corresponds to a polling interval of 65,536 clock periods (1.966 ms when clk = 33 mhz). the pollint value of 0000h is created during the microcode initialization rou tine, and therefore might not be seen when reading csr47 after h_reset or s_reset. if the user desires to program a value for pollint other than the default, the correct procedure is to first set only init in csr0. when the initialization sequence is complete, the user must set stop (csr0, bit 2) or spnd (csr5, bit 0). then the user may write to csr47 and then set strt in csr0. in this way, the default value of 0000h in csr47 will be overwritten with the de sired user value. if the user does not use the stan dard initialization procedure (standard implies use of an in itialization block in memory and setting the init bit of csr0), but instead chooses to write directly to each of the registers that are involved in the init operation, it is imperative that the user also write to csr47 as part of the al ternative initialization sequence. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr58: software style bit name description this register is an alias of the lo cation bcr20. accesses to/from this register are equivalent to ac cesses to bcr20. 31-16 res reserved locations. written as zeros and read as undefined. 15-11 res reserved locations. written as zeros and read as undefined. 10 aperren advanced parity error handling enable. when aperren is set to one, the bpe bits (rmd1 and tmd1, bit 23) are used to indicated parity error in data transfers to the receive and transmit buffers. note that since the advanced parity error han dling uses an additional bit in the descriptor, swstyle (bits 7-0 of this register) must be set to one, two or three to pro gram the pcnet pci ii controller to use 32 bit software structures. aperren does not affect the re porting of address parity errors or data parity errors that occur when the pcnet pci ii controller is the target of the transfer. read accessible always, write accessible only when either the stop or the spnd bit is set. aperren is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 9 csrpcnet csr pcnet isa configuration. when set, this bit indicates that the pcnet pci ii controller regis ter bits of csr4 and csr3 will map directly to the csr4 and csr3 bits of the pcnet isa (am79c960) device. when cleared, this bit indicates that pcnet pci ii controller register bits of csr4 and csr3 will map directly to the csr4 and csr3 bits of the ilacc (am79c900) device. the value of csrpcnet is determined by the pcnet pci ii controller according to the setting of the software style amd p r e l i m i n a r y 132 AM79C970A (swstyle, bits 7-0 of this register). read accessible always. csrpcnet is read only. write operations will be ignored. csrpcnet will be set after h_reset (since swstyle de faults to zero) and is not af fected by s_reset or by setting the stop bit. 8 ssize32 32 bit software size. when set, this bit indicates that the pcnet pci ii controller utilizes 32 bit software structures for the initialization block and the trans mit and receive descriptor en tries. when cleared, this bit indicates that the pcnet pci ii controller utilizes 16 bit software structures for the initialization block and the transmit and receive descriptor entries. in this mode the pcnet pci ii controller is backwards compatible with the am79c90 c lance and am79c960 pcnet isa. the value of ssize32 is deter mined by the pcnet pci ii con troller according to the setting of the software style (swstyle, bits 7-0 of this register). read accessible always. ssize32 is read only. write operations will be ignored. ssize32 will be cleared after h_reset (since swstyle de faults to zero) and is not affected by s_reset or by set ting the stop bit. if ssize32 is cleared to zero, then bits iadr[31:24] of csr2 will be used to generate values for the upper 8 bits of the 32 bit address bus during master accesses initiated by the pcnet pci ii controller. this action is required, since the 16 bit software structures will yield only 24 bits of address for pcnet pci ii controller bus master accesses. if ssize32 is set to one, then the software structures that are common to the pcnet pci ii con troller and the host system will supply a full 32 bits for each ad dress pointer that is needed by the pcnet pci ii controller for performing master accesses. the value of the ssize32 bit has no effect on the drive of the upper 8 address bits. the upper 8 ad dress pins are always driven, re gardless of the state of the ssize32 bit. note that the setting of the ssize32 bit has no effect on the width for i/o accesses. i/o access width is determined by the state of the dwio bit (bcr18, bit 7). 7-0 swstyle software style register. the value in this register determines the style of register and memory resources that shall be used by the pcnet pci ii controller. the software style selection will af fect the interpretation of a few bits within the csr space, the or der of the descriptor entries and the width of the descriptors and initialization block entries. all pcnet pci ii controller csr bits and bcr bits and all descrip tor, buffer and initialization block entries not cited in the table above are unaffected by the soft ware style selection. read/write accessible only when either the stop or the spnd bit is set. the swstyle register will contain the value 00h following h_reset and will be unaffected by s_reset or by setting the stop bit. p r e l i m i n a r y amd 133 AM79C970A table 25. software styles swstyle style initialization descriptor ring altered bit [7:0] name csrpcnet ssize32 block entries entries interpretations 00h c lance 1 0 16 bit software 16 bit software all bits in csr4 / structures, non burst structures, non burst are used, tmd1[29] pcnet isa or burst access access only is add_fcs 01h ilacc 0 1 32 bit software 32 bit software access csr4[9:8],csr4[5:4] structures, non burst structures, non burst and csr4[1:0] have or burst access access only no function, tmd1[29] is no_fcs. 02h pcnet 1 1 32 bit software 32 bit software all bits in csr4 are pci ii structures, non burst structures, non burst used, tmd1[29] is or burst access access only add_fcs 03h pcnet 1 1 32 bit software 32 bit software all bits in csr4 are pci ii structures, non burst structures, non burst used, tmd1[29] is controller or burst access or burst access add_fcs all other reserved undefined undefined undefined undefined undefined csr60: previous transmit descriptor address lower bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 pxdal contains the lower 16 bits of the previous transmit descriptor ad dress pointer. the pcnet pci ii controller can stack multiple transmit frames. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr61: previous transmit descriptor address upper bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 pxdau contains the upper 16 bits of the previous transmit descriptor ad dress pointer. the pcnet pci ii controller can stack multiple transmit frames. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr62: previous transmit byte count bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-12 res reserved locations. 11-0 pxbc previous transmit byte count. this field is a copy of the bcnt field of tmd1 of the previous transmit descriptor. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr63: previous transmit status bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 pxst previous transmit status. this field is a copy of bits 31-16 of tmd1 of the previous transmit descriptor. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. amd p r e l i m i n a r y 134 AM79C970A csr64: next transmit buffer address lower bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 nxbal contains the lower 16 bits of the next transmit buffer address from which the pcnet pci ii controller will transmit an outgoing frame. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr65: next transmit buffer address upper bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 nxbau contains the upper 16 bits of the next transmit buffer address from which the pcnet pci ii controller will transmit an outgoing frame. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr66: next transmit byte count bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-12 res reserved locations. read and written as zeros. 11-0 nxbc next transmit byte count. this field is a copy of the bcnt field of tmd1 of the next transmit descriptor. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr67: next transmit status bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 nxst next transmit status. this field is a copy of bits 31-16 of tmd1 of the next transmit descriptor. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. 7-0 res reserved locations. read and written as zeros. accessible only when either the stop or the spnd bit is set. csr72: receive descriptor ring counter bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 rcvrc receive descriptor ring counter location. contains a two's com plement binary number used to number the current receive de scriptor. this counter interprets the value in csr76 as pointing to the first descriptor. a counter value of zero corresponds to the last descriptor in the ring. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr74: transmit descriptor ring counter bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 xmtrc transmit descriptor ring counter location. contains a two's complement binary num ber used to number the current p r e l i m i n a r y amd 135 AM79C970A transmit descriptor. this counter interprets the value in csr78 as pointing to the first descriptor. a counter value of zero corre sponds to the last descriptor in the ring. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr76: receive descriptor ring length bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 rcvrl receive descriptor ring length. contains the two's complement of the receive descriptor ring length. this register is initialized during the pcnet pci ii controller initialization routine based on the value in the rlen field of the in itialization block. however, the ring length can be programmed to any value from 1 to 65535 by writing directly to this register. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr78: transmit descriptor ring length bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 xmtrl transmit descriptor ring length. contains the two's complement of the transmit de scriptor ring length. this register is initialized during the pcnet pci ii controller initialization rou tine based on the value in the tlen field of the initialization block. however, the ring length can be programmed to any value from 1 to 65535 by writing directly to this register. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr80: dma transfer counter and fifo watermark control bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-14 res reserved locations. read as ones and written as zeros. ac cessible only when either the stop or the spnd bit is set. 13-12rcvfw[1:0] receive fifo watermark. rcvfw specifies the number of bytes which must be present in the receive fifo (once the frame has been verified as a non runt) before receive dma is re quested. if the network interface is operating in half duplex mode, at least 64 bytes or a complete frame must be received in order for a receive dma to start. this effectively avoids having to react to receive frames which are runts or suffer a collision during the slot time (512 bit times). if the runt packet accept feature is enabled or if the network interface is oper ating in full duplex mode, receive dma will be requested as soon as either the receive fifo wa termark is reached, or a com plete valid receive frame is detected (regardless of length). if the eadi interface is active and the runt packet accept feature is enabled or the network interface is operating in full duplex mode, rcvfw must not be programmed to 00b to allow enough time to reject the frame. table 26. receive watermark programming rcvfw[1:0] bytes received 00 16 01 64 10 128 11 reserved read/write accessible only when either the stop or the spnd bit is set. rcvfw is set to a value of 01b (64 bytes) after h_reset or s_reset and is unaffected by setting the stop bit. 11-10xmtsp[1:0] transmit start point. as soon as the number of bytes in the trans mit fifo reaches the xmtsp value, the pcnet pci ii controller amd p r e l i m i n a r y 136 AM79C970A starts trying to transmit. when the entire frame is in the fifo, transmission attempts will start regardless of the value in xmtsp. if the network interface is operating in half duplex mode, regardless of xmtsp, the fifo will not internally overwrite its data until at least 64 bytes (or the entire frame if shorter than 64 bytes) have been transmitted onto the network. this ensures that for collisions within the slot time window, transmit data need not be reloaded into the transmit fifo, and retries will be handled autonomously by the mac. if the disable retry feature is enabled, or if the network is operating in full duplex mode, the pcnet pci ii controller can overwrite the be ginning of the frame as soon as the data is transmitted, because no collision handling is required in these modes. table 27. transmit start point programming xmtsp[1:0] bytes written 00 8 01 64 10 128 11 248 read/write accessible only when either the stop or the spnd bit is set. xmtsp is set to a value of 01b (64 bytes) after h_reset or s_reset and is unaffected by setting the stop bit. 9-8 xmtfw[1:0] transmit fifo watermark. xmtfw controls the point at which transmit dma is re quested. transmit dma is re quested when the number of bytes specified by xmtfw can be written to the transmit fifo. table 28. transmit watermark programming xmtfw[1:0] byte spaces available 00 16 01 64 10 128 11 reserved read/write accessible only when either the stop or the spnd bit is set. xmtfw is set to a value of 00b (16 bytes) after h_reset or s_reset and is unaffected by setting the stop bit. 7-0 dmatc[7:0] dma transfer counter. if dmaplus (csr4, bit 14) is cleared to zero, this counter contains the maximum number of fifo read or write data phases the pcnet pci ii controller will perform during a single bus mas tership period, if not preempted. the dma transfer counter is not used to limit the number of data phases during initialization block or descriptor transfers. a value of zero will be interpreted as one data phase. if dmaplus is set to one, the dma transfer counter is disabled, and the pcnet pci ii controller will try to transfer data as long as the transmit fifo is not full or as long as the receive fifo is not empty. when the pcnet pci ii controller is preempted and the last data phase has finished, dmatc will freeze. it will continue counting down when the pcnet pci ii controller is granted bus owner ship again and continues with the data transfers. dmatc should not be enabled when the pcnet pci ii controller is used in a pci bus application. the pci latency timer should be the only entity governing the time the pcnet pci ii controller has control over the bus. read/write accessible only when either the stop or the spnd bit is set. note that the read operation will yield the value of the run time copy of the dma transfer counter and not the register that holds the pro grammed value. most read op erations will yield a value of zero, because the run time counter is only reloaded with the programmed value at the be ginning of a new bus mastership period. the dma transfer counter is set to a value of 16 (10h) after h_reset or s_reset and is unaffected by setting the stop bit. p r e l i m i n a r y amd 137 AM79C970A csr82: bus activity timer bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 dmabat bus activity timer. if timer (csr4, bit 13) is set to one, this register controls the maximum allowable time that pcnet pci ii controller will take up on the sys tem bus during fifo data trans fers. the bus activity timer does not limit the time on the system bus during initialization block or descriptor transfers. the dmabat value is inter preted as an unsigned number with a resolution of 0.1 m s. for instance, a value of 51 m s would be programmed with a value of 510 (1feh). a value of zero (the default value) will result in a single data transfer. dmabat starts counting down when the pcnet pci ii controller is granted bus ownership and the bus is idle. when dmabat has counted down to zero, the pcnet pci ii controller will finish the current data phase before re leasing the bus. note that be cause dmabat does not run on the pci bus interface clock, the actual time the pcnet pci ii controller takes up the bus might differ by 2 to 3 clock periods from the value pro grammed to dmabat. dmabat should not be enabled when the pcnet pci ii controller is used in a pci bus application. the pci latency timer should be the only entity governing the time the pcnet pci ii controller has control over the bus. read/write accessible only when either the stop or the spnd bit is set. note that the read operation will yield the value of the run time copy of the bus activity timer and not the regis ter that holds the programmed value. most read operations will yield a value of zero, because the run time counter is only reloaded with the programmed value at the beginning of a new bus mastership period. the bus activity timer register is cleared to a value of 0000h after h_reset or s_reset and is unaffected by setting the stop bit. csr84: dma address register lower bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 dmabal this register contains the lower 16 bits of the address of system memory for the current dma cycle. the bus interface unit controls the address register by issuing commands to incre ment the memory address for sequential operations. the dmabal register is undefined until the first pcnet pci ii con troller dma operation. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr85: dma address register upper bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 dmabau this register contains the upper 16 bits of the address of system memory for the current dma cy cle. the bus interface unit con trols the address register by issuing commands to increment the memory address for sequen tial operations. the dmabau register is undefined until the first pcnet pci ii controller dma operation. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr86: buffer byte counter bit name description 31-16 res reserved locations. written as zeros and read as undefined. amd p r e l i m i n a r y 138 AM79C970A 15-12 res reserved locations. read and written with ones. 11-0 dmabc dma byte count register. con tains the two's complement of the remaining size of the current transmit or receive buffer in bytes. this register is incre mented by the bus interface unit. the dmabc register is unde fined until written. read/write accessible only when either the stop or the spnd bit is set. these bits are unaffected by h_reset, s_reset or by setting the stop bit. csr88: chip id register lower bit name description 31 - 28 ver version. this 4 bit pattern is sili con revision dependent. read accessible always. ver is read only. write operations are ignored. 27 - 12partid part number. the 16 bit code for the pcnet pci ii controller is 0010 0110 0010 0001b (2621h). this register is exactly the same as the device id register in the jtag description. it is, however, different from the id stored in the device id register in the pci configuration space. read accessible always. par tid is read only. write operations are ignored. 11 - 1 manfid manufacturer id. the 11 bit manufacturer code for amd is 00000000001b. this code is per the jedec publication 106 a. note that this code is not the same as the vendor id in the pci configuration space. read accessible always. manfid is read only. write op erations are ignored. 0 one always a logic one. read accessible always. one is read only. write operations are ignored. csr89: chip id register upper bit name description 31 - 16 res reserved locations. read as undefined. 15 - 12 ver version. this 4 bit pattern is sili con revision dependent. read accessible always. ver is read only. write operations are ignored. 11 - 0partidu upper 12 bits of the pcnet pci ii controller part number. i.e. 0010 0110 0010b. read accessible always. partidu is read only. write op erations are ignored. csr94: transmit time domain reflectometry count bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-10 res reserved locations. read and written as zeros. 9-0 xmttdr time domain reflectometry re flects the state of an internal counter that counts from the start of transmission to the occurrence of loss of carrier. tdr is incre mented at a rate of 10 mhz. read accessible only when either the stop or the spnd bit is set. write operations are ig nored. xmttdr is cleared by h_reset or s_reset. csr100: bus timeout bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 merrto this register contains the value of the longest allowable bus la tency (interval between assertion of req and assertion of gnt ) that a system may insert into a pcnet-pci ii controller master transfer. if this value of bus la- tency is exceeded, then merr p r e l i m i n a r y amd 139 AM79C970A (csr0, bit 11) will be set to one, and an interrupt may be gener ated, depending upon the setting of the merrm bit (csr3, bit 11) and the iena bit (csr0, bit 6). the value in this register is inter preted as the unsigned number of xtal1 clock periods divided by two, i.e. the value in this regis ter is given in 0.1 m s increments. for example, the value 0600h (1536 decimal) will cause a merr to be indicated after 153.6 m s of bus latency. a value of zero will allow an infinitely long bus latency, i.e. bus timeout error will never occur. read/write accessible only when either the stop or the spnd bit is set. this register is set to 0600h by h_reset or s_reset and is unaffected by setting the stop bit. csr112: missed frame count bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 mfc missed frame count. indicates the number of missed frames. mfc will roll over to a count of zero from the value 65535. the mfco bit (csr4, bit 8) will be set each time that this occurs. the pcnet pci ii controller will not count missed frames while the device is in suspend mode (spnd = 1, csr5, bit 0). read accessible always. mfc is read only, write operations are ignored. mfc is cleared by h_reset or s_reset or by setting the stop bit. csr114: receive collision count bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 rcc receive collision count. indi cates the total number of collisions on the network encountered by the receiver since the last reset of the counter. rcc will roll over to a count of zero from the value 65535. the rcvcco bit of csr4 (bit 5) will be set each time that this occurs. the pcnet pci ii controller will continue counting collisions on the network while the device is in suspend mode (spnd = 1, csr5, bit 0) read accessible always. rcc is read only, write operations are ig nored. rcc is cleared by h_reset or s_reset or by setting the stop bit. csr122: advanced feature control bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-2 res reserved locations. written as zeros and read as undefined. 0 rcvalgn receive frame align. when set, this bit forces the data field of iso 8802 3 (ieee/ansi 802.3) frames to align to dword ad dress boundaries. it is important to note that this feature will only function correctly if all receive buffer boundaries are dword aligned and all receive buffers have 0 mod 4 lengths. in order to accomplish the data alignment, the pcnet pci ii controller sim ply inserts two bytes of random data at the beginning of the re ceive frame (i.e. before the iso 8802 3 (ieee/ansi 802.3) desti nation address field). the mcnt field reported to the receive de scriptor will not include the extra two bytes. read/write accessible always. rcvalgn is cleared by h_reset or s_reset and is not affected by stop. csr124: test register 1 bit name description this register is used to place the pcnet pci ii controller into various test modes. only runt packet accept and gpsi port en able are user accessible test modes. all other test modes are for amd internal use only. amd p r e l i m i n a r y 140 AM79C970A table 29. gpsi mode pin configuration pcnet pci ii pcnet pci ii pcnet pci ii controller c lance controller controller expansion gpsi function gpsi i/o type gpsi pin gpsi pin pin number rom pin collision i clsn clsn 81 erd3 receive clock i rclk rxclk 85 erd1 receive data i rx rxdat 86 erd0 receive enable i rena rxen 83 erd2 transmit clock i tclk txclk 80 erd4 transmit data o tx txdat 75 erd7 transmit enable o tena txen 77 erd6 31-16 res reserved locations. written as zeros and read as undefined. 15-5 res reserved locations. written as zeros and read as undefined. 4 gpsien general purpose serial interface enable. this mode will recon figure some of the expansion rom interface pins so that the gpsi port is exposed. this allows bypassing the mendec and t mau logic. the portsel bits (csr15, bits 8-7) must be set to 10b in addition to program ming the gpsien bit in order to select the gpsi port as the active network port. read accessible always. write accessible when en124 (csr4, bit 15) is set to one. gpsien is cleared by h_reset or s_reset and is not affected by setting the stop bit. 3 rpa runt packet accept. this bit forces the pcnet pci ii controller to accept runt packets (packets shorter than 64 bytes). read accessible always. write accessible when en124 (csr4, bit 15) is set to one. rpa is cleared by h_reset or s_reset and is not affected by setting the stop bit. 2-0 res reserved locations. written as zeros and read as undefined. bus configuration registers the bus configuration registers (bcrs) are used to program the configuration of the bus interface and other special features of the pcnet pci ii controller that are not related to the ieee 8802 3 mac functions. the bcrs are accessed by first setting the appropriate rap value, and then by performing a slave access to the bdp. all bcr registers are 16 bits wide in word i/o mode (dwio = 0, bcr18, bit 7) and 32 bits wide in dword i/o mode (dwio = 1). the upper 16 bits of all bcr registers are undefined when in dword i/o mode. these bits should be written as zeros and should be treated as undefined when read. the default value given for any bcr is the value in the register after h_reset. some of these values may be changed shortly after h_reset when the contents of the external eeprom is automati cally read in. with the exception of dwio (bcr18, bit 7) bcr register values are not affected by s_reset. none of the bcr register values are affected by the as sertion of the stop bit. note that several registers have no default value. bcr0, bcr1, bcr3, bcr8, bcr10-17 and bcr21 are re served and have undefined values. the content of bcr2 is undefined until is has been first programmed through the eeprom read operation or a user register write operation. bcr0, bcr1, bcr16, bcr17 and bcr21 are registers that are used by other devices in the pcnet family. writ ing to these registers has no effect on the operation of the pcnet pci ii controller. writes to those registers marked as reserved will have no effect. reads from these locations will produce undefined values. p r e l i m i n a r y amd 141 AM79C970A table 30. bcr registers programmability rap mnemonic default name user eeprom 0 msrda 0005h reserved no no 1 mswra 0005h reserved no no 2 mc 0002h miscellaneous configuration yes yes 3 reserved n/a reserved no no 4 lnkst 00c0h link status led yes yes 5 led1 0084h led1 status yes yes 6 led2 0088h led2 status yes yes 7 led3 0090h led3 status yes yes 8 reserved n/a reserved no no 9 fdc 0000h full duplex control yes yes 10-15 reserved n/a reserved no no 16 iobasel n/a reserved no no 17 iobaseu n/a reserved no no 18 bsbc 9001h burst and bus control yes yes 19 eecas 0002h eeprom control and status yes no 20 sws 0000h software style yes no 21 intcon n/a reserved no no 22 pcilat ff06h pci latency yes yes bcr0: master mode read active bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 msrda reserved locations. after h_reset, the value in this register will be 0005h. the set ting of this register has no effect on any pcnet pci ii controller function. it is only included for software compatibility with other pcnet family devices. read always. msrda is read only write operations have no effect. bcr1: master mode write active bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 mswra reserved locations. after h_reset, the value in this reg ister will be 0005h. the setting of this register has no effect on any pcnet pci ii controller function. it is only included for software compatibility with other pcnet family devices. read always. mswra is read only write operations have no effect. bcr2: miscellaneous configuration bit name description note that bits 15-0 in this register are programmable through the external eeprom. reserved bits and read only bits should be programmed to zero. 31-16 res reserved locations. written as zeros and read as undefined. 15 res reserved location. written as zero and read as undefined. 14 tmauloop when set, this bit allows external loopback packets to pass on to the network through the t mau interface, if the t mau interface has been selected. if the t mau interface has not been selected, then this bit has no effect. amd p r e l i m i n a r y 142 AM79C970A read/write accessible always. tmauloop is cleared to zero by h_reset and is unaffected by s_reset or by setting the stop bit. 13-9 res reserved locations. written as zeros and read as undefined. 8 apromwe address prom write enable. the pcnet pci ii controller con tains a shadow ram on board for storage of the first 16 bytes loaded from the serial eeprom. accesses to address prom i/o resources will be directed toward this ram. when apromwe is set to one, then write access to the shadow ram will be enabled. read/write accessible always. apromwe is cleared to zero by h_reset and is unaffected by s_reset or by setting the stop bit. 7 intlevel interrupt level. this bit allows the interrupt output signals to be programmed for level or edge sensitive applications. when intlevel is cleared to zero, the inta pin is configured for level-sensitive applications. in this mode, an interrupt request is signaled by a low level driven on the inta pin by the pcnet-pci ii controller. when the interrupt is cleared, the inta pin is tri-stated by the pcnet-pci ii controller and allowed to be pulled to a high level by an exter- nal pullup device. this mode is intended for systems which allow the interrupt signal to be shared by multiple devices. when intlevel is set to one, the inta pin is configured for edge-sensitive applications. in this mode, an interrupt request is signaled by a high level driven on the inta pin by the pcnet-pci ii controller. when the interrupt is cleared, the inta pin is driven to a low level by the pcnet-pci ii controller. this mode is intended for systems that do not allow in- terrupt channels to be shared by multiple devices. intlevel should not be set to one when the pcnet-pci ii controller is used in a pci bus application. read/write accessible always. intlevel is cleared to zero by h_reset and is unaffected by s_reset or by setting the stop bit. 6 res reserved location. written as zero and read as undefined. 5 dxcvrctl dxcvr control. when the aui or gpsi interface is the active network port, dxcvrctl con- trols the assertion of the dxcvr output. the polarity of the as- serted state is controlled by the dxcvrpol bit (bcr2, bit 4). the dxcvr pin can be used to control a dc-to-dc converter in applications that want to connect a 10base2 mau as well as a standard db15 aui connector to the pcnet-pci ii controller aui or gpsi port. when dxcvrctl is set to one, the dxcvr output will be asserted. this could be used to enable a dc-to-dc con- verter for 10base2 maus (as- suming the enable input of the dc-to-dc converter is active high and dxcvrpol is cleared to zero). when dxcvrctl is cleared to zero, the dxcvr output will be deasserted. this would power down the dc-to-dc converter. when the 10base-t interface is the active network port, the dxcvr output is always deasserted. read/write accessible always. dxcvrctl is cleared by h_reset and is unaffected by s_reset or by setting the stop bit. 4 dxcvrpol dxcvr polarity. this bit controls the polarity of the asserted state of the dxcvr output. when dxcvrpol is cleared to zero, the dxcvr output will be high when asserted. when dxcvrpol is set to one, the dxcvr output will be low when asserted. p r e l i m i n a r y amd 143 AM79C970A table 31. dxcvr output control active dxcvr dxcvrctl dxcvrpol network port output x 0 10base t low x 1 10base t high 0 0 aui or gpsi low 1 0 aui or gpsi high 0 1 aui or gpsi high 1 1 aui or gpsi low read/write accessible always. dxcvrpol is cleared by h_reset and is unaffected by s_reset or by setting the stop bit. 3 eadisel eadi select. when set to one, this bit enables the three eadi in terface pins that are multiplexed with other functions. eesk/ led1 becomes sfbd, eedo/ led3 becomes srd, and led2 be- comes srdclk. read/write accessible always. eadisel is cleared by h_reset and is unaffected by s_reset or by setting the stop bit. 2 awake this bit selects one of two differ- ent sleep modes. if awake is set to one and the sleep pin is asserted, the pcnet-pci ii controller goes into snooze mode. if awake is cleared to zero and the sleep pin is asserted, the pcnet-pci ii controller goes into coma mode. see the section power saving modes for more details. this bit only has meaning when the 10base-t network interface is selected. read/write accessible always. awake is cleared to zero by h_reset and is unaffected by s_reset or by setting the stop bit. 1 asel auto select. when set, the pcnet-pci ii controller will auto- matically select the operating media interface port, unless the user has selected gpsi mode through appropriate program- ming of the portsel bits of the mode register (csr15). if gpsi mode has not been selected, asel has been set to one, and the 10base-t transceiver is in the link pass state, the 10base-t port will be used. if gpsi mode has not been se- lected, asel has been set to one, and the 10base-t port is in the link fail state, the aui port will be used. if one of the above conditions changes during trans- mission, switching between the ports will not occur until the trans- mission is ended. when asel is set to one, link beat pulses will be transmitted on the 10base-t port, regard- less of the state of link status. when asel is cleared to zero, link beat pulses will only be transmitted on the 10base-t port when the portsel bits of the mode register (csr15) have selected 10base-t as the active port. when asel is cleared to zero, then the selected network port will be determined by the settings of the portsel bits of csr15. read/write accessible always. asel is set to one by h_reset and is unaffected by s_reset or by setting the stop bit. the network port configurations are as follows: table 32. network port configuration asel link status network portsel[1:0] (bcr2[1]) (of 10base-t) port 0x 1 fail aui 0x 1 pass 10base-t 00 0 x aui 01 0 x 10base-t 10 x x gpsi 11 x x reserved 0 xmausel reserved location. read/write accessible always. this reserved location is cleared by h_reset and is unaffected by s_reset or by setting the stop bit. writ- ing a one to this bit has no effect on the operation of the pcnet-pci ii controller. amd p r e l i m i n a r y 144 AM79C970A bcr4: link status led (lnkst) bit name description bcr4 determines which func tion(s) activate the lnkst pin. the pin will indicate the logical or of the enabled functions. bcr4 defaults to link status (lnkst) with pulse stretcher nabled (pse = 1). note that bits 15C0 in this register are programmable through the external eeprom. reserved bits and read-only bits should be programmed to zero. 31C16 res reserved locations. written as zeros and read as undefined. 15 ledout this bit indicates the current (non-stretched) value of the led output pin. a value of one in this bit indicates that the or of the enabled signals is true. the logical value of the ledout status signal is determined by the settings of the individual status enable bits of this register (bits 8 and 6C0). read accessible always. this bit is read only. writes have no ef- fect. ledout is unaffected by h_reset, s_reset or by set- ting the stop bit. 14 ledpol led polarity. when this bit has the value zero, the led pin will be asserted low whenever the or of the enabled signals is true, and the led pin will be disabled and allowed to float whenever the or of the enabled signals is false. (the led output will be an open drain output, and the output value will be the inverse of the ledout status bit.) when this bit has the value one, the led pin will be asserted high whenever the or of the enabled signals is true, and the led pin will be driven to a low level whenever the or of the en- abled signals is false. (the led output will be a totem pole output, and the output value will be the same polarity as the ledout status bit.) the setting of this bit will not ef- fect the polarity of the ledout bit for this register. read/write accessible always. ledpol is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 13 leddis led disable. this bit is used to disable the led output. when leddis is set to one and ledpol is cleared to zero, the led output pin will be floating. when leddis is set to one and ledpol is set to one, the led output pin will be driven low. when leddis has the value zero, the led output value will be governed by the ledout and ledpol values. read/write accessible always. leddis is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 12C10 res reserved locations. written as zeros and read as undefined. 9 mpse magic packet status enable. when this bit is set to one, a value of one is passed to the ledout bit in this register when magic packet mode is enabled and a magic packet is detected on the network. read/write accessible always. mpse is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 8 fdlse full-duplex link status enable. indicates the full-duplex link test status. when this bit is set to one, a value of one is passed to the ledout signal when the pcnet-pci ii controller is functioning in a link pass state and full-duplex operation is en- abled. when the pcnet-pci ii controller is not functioning in a link pass state with full-duplex operation being enabled, a value of zero is passed to the ledout signal. when the 10base-t port is ac- tive, a value of one is passed to the ledout signal whenever the link test function detects a link pass state and the fden (bcr9, bit 0) bit is set. when the aui port is active, a value of one is passed to the ledout signal whenever full-duplex operation on the aui port is enabled (both fden and auifd bits in bcr9 are set to one). when the gpsi p r e l i m i n a r y amd 145 AM79C970A port is active, a value of one is passed to the ledout signal whenever full duplex operation on the gpsi port is enabled (fden bit in bcr9 is set to one). read/write accessible always. fdlse is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 7 pse pulse stretcher enable. when this bit is set to one, the led illu mination time is extended so that brief occurrences of the enabled function will be seen on this led output. a value of zero disables the pulse stretcher. read/write accessible always. pse is set to one by h_reset and is not affected by s_reset or by setting the stop bit. 6 lnkste link status enable. when this bit is set to one, a value of one will be passed to the ledout bit in this register when the t mau op erating in half duplex mode is in link pass state. when the t mau operating in half duplex mode is in link fail state, a value of zero is passed to the ledout bit. the function of this bit is masked if the 10base t port is operating in full duplex mode. this allows a system to have separate leds for half duplex link status and for full duplex link status. read/write accessible always. lnkste is set to one by h_reset and is not affected by s_reset or by setting the stop bit. 5 rcvme receive match status enable. when this bit is set to one, a value of one is passed to the ledout bit in this register when the there is receive activity on the network that has passed the ad dress match function for this node. all address matching modes are included: physical, logical filtering, broadcast and promiscuous. read/write accessible always. rcvme is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 4 xmte transmit status enable. when this bit is set to one, a value of one is passed to the ledout bit in this register when there is transmit activity on the network. read/write accessible always. xmte is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 3 rxpole receive polarity status enable. when this bit is set to one, a value of one is passed to the ledout bit in this register when the polarity of the rxd pair is not reversed. receive polarity indication is valid only if the t mau is in link pass state. read/write accessible always. rxpole is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 2 rcve receive status enable. when this bit is set to one, a value of one is passed to the ledout bit in this register when there is receive activity on the network. read/write accessible always. rcve is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 1 jabe jabber status enable. when this bit is set to one, a value of one is passed to the ledout bit in this register when the pcnet pci ii controller is jabber ing on the network. read/write accessible always. jabe is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 0 cole collision status enable. when this bit is set to one, a value of one is passed to the ledout bit in this register when there is collision activity on the network. the activity on the collision in puts to the aui or gpsi ports within the first 4 m s after every transmission for the purpose of sqe testing will not cause the ledout bit to be set. read/write accessible always. cole is cleared by h_reset amd p r e l i m i n a r y 146 AM79C970A and is not affected by s_reset or by setting the stop bit. bcr5: led1 status bit name description bcr5 determines which func tion(s) activate the led1 pin. the pin will indicate the logical or of the enabled functions. bcr5 defaults to receive status (rcv) with pulse stretcher enabled (pse = 1). note that bits 15C0 in this register are programmable through the external eeprom. reserved bits and read-only bits should be programmed to zero. 31C16 res reserved locations. written as zeros and read as undefined. 15 ledout this bit indicates the current (non-stretched) value of the led output pin. a value of one in this bit indicates that the or of the enabled signals is true. the logical value of the ledout status signal is determined by the settings of the individual status enable bits of this register (bits 8 and 6C0). read accessible always. this bit is read only. writes have no ef- fect. ledout is unaffected by h_reset, s_reset or by set- ting the stop bit. 14 ledpol led polarity. when this bit has the value zero, the led pin will be asserted low whenever the or of the enabled signals is true, and the led pin will be disabled and allowed to float whenever the or of the enabled signals is false. (the led output will be an open drain output, and the output value will be the inverse of the ledout status bit.) when this bit has the value one, the led pin will be asserted high whenever the or of the enabled signals is true, and the led pin will be driven to a low level whenever the or of the en- abled signals is false. (the led output will be a totem pole output, and the output value will be the same polarity as the ledout status bit.) the setting of this bit will not ef- fect the polarity of the ledout bit for this register. read/write accessible always. ledpol is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 13 leddis led disable. this bit is used to disable the led output. when leddis is set to one and ledpol is cleared to zero, the led output pin will be floating. when leddis is set to one and ledpol is set to one, the led output pin will be driven low. when leddis has the value zero, the led output value will be governed by the ledout and ledpol values. read/write accessible always. leddis is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 12C10 res reserved locations. written as zeros and read as undefined. 9 mpse magic packet status enable. when this bit is set to one, a value of one is passed to the ledout bit in this register when magic packet mode is enabled and a magic packet is detected on the network. read/write accessible always. mpse is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 8 fdlse full-duplex link status enable. indicates the full-duplex link test status. when this bit is set to one, a value of one is passed to the ledout signal when the pcnet-pci ii controller is functioning in a link pass state and full-duplex operation is en- abled. when the pcnet-pci ii controller is not functioning in a link pass state with full-duplex operation being enabled, a value of zero is passed to the ledout signal. when the 10base-t port is ac- tive, a value of one is passed to the ledout signal whenever the link test function detects a link pass state and the fden (bcr9, bit 0) bit is set. when the aui port is active, a value of one p r e l i m i n a r y amd 147 AM79C970A is passed to the ledout signal whenever full duplex operation on the aui port is enabled (both fden and auifd bits in bcr9 are set to one). when the gpsi port is active, a value of one is passed to the ledout signal whenever full duplex op eration on the gpsi port is en abled (fden bit in bcr9 is set to one). read/write accessible always. fdlse is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 7 pse pulse stretcher enable. when this bit is set to one, the led illu mination time is extended so that brief occurrences of the enabled function will be seen on this led output. a value of zero disables the pulse stretcher. read/write accessible always. pse is set to one by h_reset and is not affected by s_reset or by setting the stop bit. 6 lnkste link status enable. when this bit is set to one, a value of one will be passed to the ledout bit in this register when the t mau op erating in half duplex mode is in link pass state. when the t mau operating in half duplex mode is in link fail state, a value of zero is passed to the ledout bit. the function of this bit is masked if the 10base t port is operating in full duplex mode. this allows a system to have separate leds for half duplex link status and for full duplex link status. read/write accessible always. lnkste is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 5 rcvme receive match status enable. when this bit is set to one, a value of one is passed to the ledout bit in this register when the there is receive activity on the network that has passed the address match function for this node. all address matching modes are included: physical, logical filtering, broad cast and promiscuous. read/write accessible always. rcvme is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 4 xmte transmit status enable. when this bit is set to one, a value of one is passed to the ledout bit in this register when there is transmit activity on the network. read/write accessible always. xmte is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 3 rxpole receive polarity status enable. when this bit is set to one, a value of one is passed to the ledout bit in this register when the polarity of the rxd pair is not reversed. receive polarity indication is valid only if the t mau is in link pass state. read/write accessible always. rxpole is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 2 rcve receive status enable. when this bit is set to one, a value of one is passed to the ledout bit in this register when there is receive activity on the network. read/write accessible always. rcve is set to one by h_reset and is not affected by s_reset or by setting the stop bit. 1 jabe jabber status enable. when this bit is set to one, a value of one is passed to the ledout bit in this register when the pcnet pci ii controller is jabber ing on the network. read/write accessible always. jabe is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 0 cole collision status enable. when this bit is set to one, a value of one is passed to the ledout bit in this register when there is collision activity on the network. the activity on the collision inputs to the aui or gpsi ports within the first 4 m s after every amd p r e l i m i n a r y 148 AM79C970A transmission for the purpose of sqe testing will not cause the ledout bit to be set. read/write accessible always. cole is cleared by h_reset and is not affected by s_reset or by setting the stop bit. bcr6: led2 status bit name description bcr6 determines which func tion(s) activate the led2 pin. the pin will indicate the logical or of the enabled functions. bcr6 de- faults to receive polarity status (rxpol) with pulse stretcher enabled (pse = 1). note that bits 15C0 in this register are programmable through the external eeprom. reserved bits and read-only bits should be programmed to zero. 31C16 res reserved locations. written as zeros and read as undefined. 15 ledout this bit indicates the current (non-stretched) value of the led output pin. a value of one in this bit indicates that the or of the enabled signals is true. the logical value of the ledout status signal is determined by the settings of the individual status enable bits of this register (bits 8 and 6C0). read accessible always. this bit is read only. writes have no ef- fect. ledout is unaffected by h_reset, s_reset or by set- ting the stop bit. 14 ledpol led polarity. when this bit has the value zero, the led pin will be asserted low whenever the or of the enabled signals is true, and the led pin will be disabled and allowed to float whenever the or of the enabled signals is false. (the led output will be an open drain output, and the output value will be the inverse of the ledout status bit.) when this bit has the value one, the led pin will be asserted high whenever the or of the enabled signals is true, and the led pin will be driven to a low level whenever the or of the en- abled signals is false. (the led output will be a totem pole output, and the output value will be the same polarity as the ledout status bit.) the setting of this bit will not ef- fect the polarity of the ledout bit for this register. read/write accessible always. ledpol is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 13 leddis led disable. this bit is used to disable the led output. when leddis is set to one and ledpol is cleared to zero, the led output pin will be floating. when leddis is set to one and ledpol is set to one, the led output pin will be driven low. when leddis has the value zero, the led output value will be governed by the ledout and ledpol values. read/write accessible always. leddis is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 12C10 res reserved locations. written as zeros and read as undefined. 9 mpse magic packet status enable. when this bit is set to one, a value of one is passed to the ledout bit in this register when magic packet mode is enabled and a magic packet is detected on the network. read/write accessible always. mpse is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 8 fdlse full-duplex link status enable. indicates the full-duplex link test status. when this bit is set to one, a value of one is passed to the ledout signal when the pcnet-pci ii controller is functioning in a link pass state and full-duplex operation is en- abled. when the pcnet-pci ii controller is not functioning in a link pass state with full-duplex operation being enabled, a value of zero is passed to the ledout signal. when the 10base-t port is ac- tive, a value of one is passed to p r e l i m i n a r y amd 149 AM79C970A the ledout signal whenever the link test function detects a link pass state and the fden (bcr9, bit 0) bit is set. when the aui port is active, a value of one is passed to the ledout signal whenever full duplex operation on the aui port is enabled (both fden and auifd bits in bcr9 are set to one). when the gpsi port is active, a value of one is passed to the ledout signal whenever full duplex operation on the gpsi port is enabled (fden bit in bcr9 is set to one). read/write accessible always. fdlse is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 7 pse pulse stretcher enable. when this bit is set to one, the led illu mination time is extended so that brief occurrences of the enabled function will be seen on this led output. a value of zero disables the pulse stretcher. read/write accessible always. pse is set to one by h_reset and is not affected by s_reset or by setting the stop bit. 6 lnkste link status enable. when this bit is set to one, a value of one will be passed to the ledout bit in this register when the t mau op erating in half duplex mode is in link pass state. when the t mau operating in half duplex mode is in link fail state, a value of zero is passed to the ledout bit. the function of this bit is masked if the 10base t port is operating in full duplex mode. this allows a system to have separate leds for half duplex link status and for full duplex link status. read/write accessible always. lnkste is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 5 rcvme receive match status enable. when this bit is set to one, a value of one is passed to the ledout bit in this register when the there is receive activity on the network that has passed the ad dress match function for this node. all address matching modes are included: physical, logical filtering, broadcast and promiscuous. read/write accessible always. rcvme is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 4 xmte transmit status enable. when this bit is set to one, a value of one is passed to the ledout bit in this register when there is transmit activity on the network. read/write accessible always. xmte is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 3 rxpole receive polarity status enable. when this bit is set to one, a value of one is passed to the ledout bit in this register when the polarity of the rxd pair is not reversed. receive polarity indication is valid only if the t mau is in link pass state. read/write accessible always. rxpole is set to one by h_reset and is not affected by s_reset or by setting the stop bit. 2 rcve receive status enable. when this bit is set to one, a value of one is passed to the ledout bit in this register when there is receive activity on the network. read/write accessible always. rcve is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 1 jabe jabber status enable. when this bit is set to one, a value of one is passed to the ledout bit in this register when the pcnet pci ii controller is jabber ing on the network. read/write accessible always. jabe is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 0 cole collision status enable. when this bit is set to one, a value of one is passed to the ledout bit in this register when there is collision activity on the network. the activity on the collision in puts to the aui or gpsi ports amd p r e l i m i n a r y 150 AM79C970A within the first 4 m s after every transmission for the purpose of sqe testing will not cause the ledout bit to be set. read/write accessible always. cole is cleared by h_reset and is not affected by s_reset or by setting the stop bit. bcr7: led3 status bit name description bcr7 determines which func tion(s) activate the led3 pin. the pin will indicate the logical or of the enabled functions. bcr7 defaults to transmit status (xmt) with pulse stretcher enabled (pse = 1). note that bits 15C0 in this register are programmable through the external eeprom. reserved bits and read-only bits should be programmed to zero. 31C16 res reserved locations. written as zeros and read as undefined. 15 ledout this bit indicates the current (non-stretched) value of the led output pin. a value of one in this bit indicates that the or of the enabled signals is true. the logical value of the ledout status signal is determined by the settings of the individual status enable bits of this register (bits 8 and 6C0). read accessible always. this bit is read only. writes have no ef- fect. ledout is unaffected by h_reset, s_reset or by set- ting the stop bit. 14 ledpol led polarity. when this bit has the value zero, the led pin will be asserted low whenever the or of the enabled signals is true, and the led pin will be disabled and allowed to float whenever the or of the enabled signals is false. (the led output will be an open drain output, and the output value will be the inverse of the ledout status bit.) when this bit has the value one, the led pin will be asserted high whenever the or of the enabled signals is true, and the led pin will be driven to a low level whenever the or of the enabled signals is false. (the led output will be a totem pole output, and the output value will be the same polarity as the ledout status bit.) the setting of this bit will not ef- fect the polarity of the ledout bit for this register. read/write accessible always. ledpol is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 13 leddis led disable. this bit is used to disable the led output. when leddis is set to one and ledpol is cleared to zero, the led output pin will be floating. when leddis is set to one and ledpol is set to one, the led output pin will be driven low. when leddis has the value zero, the led output value will be governed by the ledout and ledpol values. read/write accessible always. leddis is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 12C10 res reserved locations. written as zeros and read as undefined. 9 mpse magic packet status enable. when this bit is set to one, a value of one is passed to the ledout bit in this register when magic packet mode is enabled and a magic packet is detected on the network. read/write accessible always. mpse is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 8 fdlse full-duplex link status enable. indicates the full-duplex link test status. when this bit is set to one, a value of one is passed to the ledout signal when the pcnet-pci ii controller is functioning in a link pass state and full-duplex operation is en- abled. when the pcnet-pci ii controller is not functioning in a link pass state with full-duplex operation being enabled, a value of zero is passed to the ledout signal. when the 10base-t port is ac- tive, a value of one is passed to p r e l i m i n a r y amd 151 AM79C970A the ledout signal whenever the link test function detects a link pass state and the fden (bcr9, bit 0) bit is set. when the aui port is active, a value of one is passed to the ledout signal whenever full duplex operation on the aui port is enabled (both fden and auifd bits in bcr9 are set to one). when the gpsi port is active, a value of one is passed to the ledout signal whenever full duplex operation on the gpsi port is enabled (fden bit in bcr9 is set to one). read/write accessible always. fdlse is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 7 pse pulse stretcher enable. when this bit is set to one, the led illu mination time is extended so that brief occurrences of the enabled function will be seen on this led output. a value of zero disables the pulse stretcher. read/write accessible always. pse is set to one by h_reset and is not affected by s_reset or by setting the stop bit. 6 lnkste link status enable. when this bit is set to one, a value of one will be passed to the ledout bit in this register when the t mau op erating in half duplex mode is in link pass state. when the t mau operating in half duplex mode is in link fail state, a value of zero is passed to the ledout bit. the function of this bit is masked if the 10base t port is operating in full duplex mode. this allows a system to have separate leds for half duplex link status and for full duplex link status. read/write accessible always. lnkste is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 5 rcvme receive match status enable. when this bit is set to one, a value of one is passed to the ledout bit in this register when the there is receive activity on the network that has passed the ad dress match function for this node. all address matching modes are included: physical, logical filtering, broadcast and promiscuous. read/write accessible always. rcvme is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 4 xmte transmit status enable. when this bit is set to one, a value of one is passed to the ledout bit in this register when there is transmit activity on the network. read/write accessible always. xmte is set to one by h_reset and is not affected by s_reset or by setting the stop bit. 3 rxpole receive polarity status enable. when this bit is set to one, a value of one is passed to the ledout bit in this register when the polarity of the rxd pair is not reversed. receive polarity indication is valid only if the t mau is in link pass state. read/write accessible always. rxpole is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 2 rcve receive status enable. when this bit is set to one, a value of one is passed to the ledout bit in this register when there is receive activity on the network. read/write accessible always. rcve is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 1 jabe jabber status enable. when this bit is set to one, a value of one is passed to the ledout bit in this register when the pcnet pci ii controller is jabbering on the network. read/write accessible always. jabe is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 0 cole collision status enable. when this bit is set to one, a value of one is passed to the ledout bit in this register when there is collision activity on the network. the activity on the collision amd p r e l i m i n a r y 152 AM79C970A inputs to the aui or gpsi ports within the first 4 m s after every transmission for the purpose of sqe testing will not cause the ledout bit to be set. read/write accessible always. cole is cleared by h_reset and is not affected by s_reset or by setting the stop bit. bcr9: full duplex control bit name description note that bits 15-0 in this register are programmable through the external eeprom. reserved bits and read only bits should be programmed to zero. 31-16 res reserved locations. written as zeros and read as undefined. 15-3 res reserved locations. written as zeros and read as undefined. 2 fdrpad full duplex runt packet accept disable. when fdrpad is set to one and full duplex mode is en abled, the pcnet pci ii controller will only receive frames that meet the minimum ethernet frame length of 64 bytes. receive dma will not start until at least 64 bytes or a complete frame have been received. by default, fdrpad is cleared to zero. the pcnet pci ii controller will accept any length frame and receive dma will start according to the pro gramming of the receive fifo watermark. note that there should not be any runt packets in a full duplex network, since the main cause for runt packets is a network collision and there are no collisions in a full duplex net work. read/write accessible always. fdrpad is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 1 auifd aui full duplex. auifd enables full duplex operation on the aui port. auifd is only meaningful if fden (bcr9, bit 0) is set to one. if the fden bit is zero, the aui port will always operate in half duplex mode. if fden is set to one and auifd is set to one, full duplex operation on the aui port is enabled. however, if fden is set to one but the auifd bit is cleared to zero, the aui port will always operate in half duplex mode. read/write accessible always. auifd is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 0 fden full duplex enable. fden en ables full duplex operation. when fden is set to one, the pcnet pci ii controller will oper ate in full duplex mode when either the 10base t or the gpsi port is enabled. to enable full duplex operation on the aui port, the auifd bit (bcr9, bit1) must be set to one in addition to set ting fden to one. when the dlnktst bit (csr15, bit 12) is set to one, the 10base t port will operate in half duplex mode regardless of the setting of fden. effect on the auifd fden effect on the 10base t effect on the (bit 1) (bit 0) aui port port gpsi port x 0 half duplex half duplex half duplex 0 1 half duplex full duplex full duplex 1 1 full duplex full duplex full duplex read/write accessible always. fden is cleared by h_reset and is not affected by s_reset or by setting the stop bit. bcr16: i/o base address lower bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-5 iobasel reserved locations. after h_reset, the value of these bits will be undefined. the settings of these bits will have no effect on any pcnet pci ii controller function. it is only in cluded for software compatibility with other pcnet family devices. read/write accessible always. iobasel is not affected by s_reset or by setting the stop bit. 4-0 res reserved locations. written as zeros, read as undefined. p r e l i m i n a r y amd 153 AM79C970A bcr17: i/o base address upper bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 iobaseu reserved locations. after h_reset, the value in this register will be undefined. the setting of this register has no ef? fect on any pcnet?pci ii control? ler function. it is only included for software compatibility with other pcnet family devices. read/write accessible always. iobaseu is not affected by s_reset or by setting the stop bit. bcr18: burst and bus control register bit name description note that bits 15-0 in this register are programmable through the external eeprom. reserved bits and read?only bits should be programmed to zero. 31-16 res reserved locations. written as zeros and read as undefined. 15-12romtmg expansion rom timing. the value of romtmg is used to tune the timing of the expansion rom interface. romtmg de? fines the time from when the pcnet?pci ii controller drives era[7:0] with the lower 8?bits of the expansion rom address to when the pcnet?pci ii controller latches in the data on the erd[7:0] inputs. the register value specifies the time in num? ber of clock cycles. a romtmg value of zero results in the same timing as a romtmg value of one. the access time for the expan? sion rom device (t acc ) can be calculated by subtracting the clock to output delay for the era[7:0] outputs (t val (era)) and the input to clock setup time for the erd[7:0] inputs (t su (erd)) from the time defined by romtmg: t acc romtmg * clock period - t val (era) - t su (erd) for an adapter card application, the value used for clock period should be 30 ns to guarantee cor rect interface timing at the maxi mum clock frequency of 33 mhz. read accessible always. write accessible only when either the stop or the spnd bit is set. romtmg is set to the value of 1001b by h_reset and is not affected by s_reset or by setting the stop bit. the default value allows using an expansion rom with an access time of 250 ns in a system with a maximum clock frequency of 33 mhz. 11-10 res reserved locations. written as zeros and read as undefined. 9 memcmd memory command. this bit de termines the command code used for burst read accesses to transmit buffers. when memcmd is cleared to zero, all burst read accesses to trans mit buffers are of the pci com mand type memory read line (type 14). when memcmd is set to one, all burst read accesses to transmit buffers are of the pci command type memory read multiple (type 12). read accessible always. write accessible only when either the stop or the spnd bit is set. memcmd is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 8 extreq extended request. this bit controls the deassertion of req for a burst transaction. if ex- treq is cleared to zero, req is deasserted at the beginning of a burst transaction. (the pcnet- pci ii controller never performs more than one burst transaction within a single bus mastership period.) in this mode, the pcnet- pci ii controller relies on the pci latency timer to get enough bus bandwidth, in case the system arbiter also removes gnt at the beginning of the burst transac- tion. if extreq is set to one, req stays asserted until the next to last data phase of the burst transaction is done. this mode is useful for systems that imple- ment an arbitration scheme with- out preemption and require that req stays asserted throughout the transaction. amd p r e l i m i n a r y 154 AM79C970A extreq should not be set to one when the pcnet pci ii controller is used in a pci bus application. read accessible always. write accessible only when either the stop or the spnd bit is set. extreq is cleared by h_reset and or s_reset and is not affected by setting the stop bit. 7 dwio double word i/o. when set, this bit indicates that the pcnet pci ii controller is programmed for dword i/o (dwio) mode. when cleared, this bit indicates that the pcnet pci ii controller is pro grammed for word i/o (wio) mode. this bit affects the i/o resource offset map and it af fects the defined width of the pcnet pci ii controller's i/o re sources. see the sections word i/o mode" and double word i/o mode" for more details. read accessible always. dwio is cleared by h_reset and is not affected by s_reset or by setting the stop bit. dwio is cleared by h_reset or s_re set and is not affected by setting the stop bit. 6 breade burst read enable. when set, this bit enables burst mode dur ing memory read accesses. the pcnet pci ii controller can per form burst transfers when read ing the initialization block, the descriptor ring entries (when swstyle is set to three), and the buffer memory. when cleared, this bit prevents the device from bursting during read accesses. breade should be set to one when the pcnet pci ii controller is used in a pc bus application to guarantee maximum performance. read accessible always. write accessible only when either the stop or the spnd bit is set. breade is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 5 bwrite burst write enable. when set, this bit enables burst mode during memory write accesses. the pcnet pci ii controller can perform burst transfers when writing the descriptor ring entries (when swstyle is set to three) and the buffer memory. when cleared, this bit prevents the device from bursting during write accesses. bwrite should be set to one when the pcnet pci ii con troller is used in a pci bus application to guarantee maximum performance. read accessible always. write accessible only when either the stop or the spnd bit is set. bwrite is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 4-3 tstshdw reserved locations. written and read as zeros. 2-0 linbc reserved locations. read acces sible always. write accessible only when either the stop or the spnd bit is set. after h_reset, the value in these bits will be 001b. the setting of these bits has no effect on any pcnet pci ii controller function. linbc is not affected by s_reset or by set ting the stop bit. bcr19: eeprom control and status bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15 pvalid eeprom valid status bit. a value of one in this bit indicates that a pread operation has oc curred, and that (1) there is an eeprom connected to the pcnet pci ii controller microwire interface pins and (2) the con tents read from the eeprom have passed the checksum veri fication operation. a value of zero in this bit indicates that the checksum for the entire 36 bytes of eeprom is incorrect or that no eeprom is connected to the microwire interface pins. if pvalid becomes zero following an eeprom read op eration (either automatically generated after h_reset, or requested through pread), then all eeprom programma p r e l i m i n a r y amd 155 AM79C970A ble bcr locations will be reset to their h_reset values. the contents of the address prom locations, however, will not be cleared. if the eeprom detection fails, then all attempted pread commands will terminate early and pvalid will not be set. this applies to the automatic read of the eeprom after h_reset as well as to host initiated pread commands. read accessible only. pvalid is read only. write operations have no effect. pvalid is cleared to zero during h_reset and is unaffected by s_reset or by setting the stop bit. 14 pread eeprom read command bit. when this bit is set to one by the host, the pvalid bit (bcr19, bit 15) will immediately be cleared to zero and then the pcnet pci ii controller will perform a read op eration of 36 bytes from the eeprom through the microwire interface. the eeprom data that is fetched during the read will be stored in the appropriate internal registers on board the pcnet pci ii controller. eeprom contents will be indi rectly accessible to the host through read accesses to the ad dress prom (offsets 0h through fh) and through read accesses to the eeprom programmable bcrs. note that read accesses from these locations will not actu ally access the eeprom itself, but instead will access the pcnet pci ii controller's internal copy of the eeprom contents. write accesses to these loca tions may change the pcnet pci ii controller register contents, but the eeprom locations will not be affected. eeprom locations may also be accessed directly by programming bits 4-0 of this register. at the end of the read operation, the pread bit will automatically be cleared to zero by the pcnet pci ii controller and pvalid will be set, provided that an eeprom existed on the microwire interface pins and that the checksum for the entire 36 bytes of eeprom was correct. note that when pread is set to one, the pcnet pci ii controller will no longer respond to any ac cesses directed toward it, until the pread operation has completed successfully. the pcnet pci ii controller will termi nate these accesses with the assertion of devsel and stop while trdy is not asserted, sig- naling to the initiator to discon- nect and retry the access at a later time. if a pread command is given to the pcnet-pci ii controller but no eeprom is detected at the microwire interface pins, the pread command will terminate early, the pread bit will be cleared to zero, the pvalid bit will remain zero, and all eeprom-programmable bcr locations will be reset to their h_reset values. the contents of the address prom locations, however, will not be cleared. read accessible always. write accessible only when either the stop or the spnd bit is set. pread is cleared to zero dur- ing h_reset and is unaffected by s_reset or by setting the stop bit. 13 eedet eeprom detect. this bit indi- cates the sampled value of the eesk/ led1 /sfbd pin at the ris- ing edge of clk during the last clock during which rst is as- serted. this value indicates whether or not an eeprom has been detected at the eeprom interface. if this bit is a one, it in- dicates that an eeprom has been detected. if this bit is a zero, it indicates that an eeprom has not been detected. read accessible always. eedet is read only. write operations have no effect. it is unaffected by s_reset or by setting the stop bit. the following table indicates the possible combinations of eedet and the existence of an eeprom and the resulting op- erations that are possible on the eeprom microwire interface: amd p r e l i m i n a r y 156 AM79C970A table 33. eedet setting eedet value eeprom result of automatic eeprom read (bcr19[3]) connected? result if pread is set to one operation following h_reset 0 no eeprom read operation is attempted. first two eesk clock cycles are entire read sequence will occur, generated, then eeprom read checksum failure will result, pvalid operation is aborted and pvalid is cleared to zero. is cleared to zero. 0 yes eeprom read operation is attempted. first two eesk clock cycles are entire read sequence will occur, generated, then eeprom read checksum operation will pass, pvalid operation is aborted and pvalid is is set to one. cleared to zero. 1 no eeprom read operation is attempted. eeprom read operation is attempted. entire read sequence will occur, entire read sequence will occur, checksum failure will result, pvalid checksum failure will result, pvalid is is cleared to zero. cleared to zero. 1 yes eeprom read operation is attempted. eeprom read operation is attempted. entire read sequence will occur, entire read sequence will occur, checksum operation will pass, pvalid checksum operation will pass, pvalid is set to one. is set to one. 12-5 res reserved locations. written as zeros, read as undefined. 4 een eeprom port enable. when this bit is set to one, it causes the values of ecs, esk, and edi to be driven onto the eecs, eesk, and eedi pins, respectively. if een is cleared to zero and no eeprom read function is currently active, then eecs will be driven low and the eesk and eedi pins change their function to led1 and lnkst and are controlled by bcr5 and bcr4, respectively. read accessible always. write accessible only when either the stop or the spnd bit is set. een is cleared to zero by h_reset and is unaffected by s_reset or by setting the stop bit. 3 res reserved location. written as zero and read as undefined. 2 ecs eeprom chip select. this bit is used to control the value of the eecs pin of the microwire inter- face when the een bit is set to one and the pread bit is cleared to zero. if een is set to one and pread is cleared to zero and ecs is set to one, then the eecs pin will be forced to a high level at the rising edge of the next clock following bit pro- gramming. if een is set to one and pread is cleared to zero and ecs is cleared to zero, then the eecs pin will be forced to a low level at the rising edge of the next clock following bit pro- gramming. ecs has no effect on the output value of the eecs pin unless the pread bit is cleared to zero and the een bit is set to one. read accessible always. write accessible only when either the stop or the spnd bit is set. ecs is cleared to zero by h_reset and is not affected by s_reset or by setting the stop bit. 1 esk eeprom serial clock. this bit and the edi/edo bit are used to control host access to the eeprom. values programmed to this bit are placed on to the eesk pin at the rising edge of the next clock following bit program- ming, except when the pread bit is set to one or the een bit is cleared to zero. if both the esk bit and the edi/edo bit values are changed during one bcr19 write operation while een is set to one, then setup and hold times of the eedi pin value with respect to the eesk signal edge are not guaranteed. esk has no effect on the eesk pin unless the pread bit is cleared to zero and the een bit is set to one. p r e l i m i n a r y amd 157 AM79C970A table 34. microwire interface pin assignment pread or auto read in rst pin progress een eecs eesk eedi high x x low tri-state tri-state low 1 x active active active low 0 1 bcr19[2] bcr19[1] bcr19[0] low 0 0 low led1 lnkst read accessible always. write accessible only when either the stop or the spnd bit is set. esk is set to one by h_reset and is not affected by s_reset or by setting the stop bit. 0 edi/edo eeprom data in/eeprom data out. data that is written to this bit will appear on the eedi output of the microwire interface, except when the pread bit is set to one or the een bit is cleared to zero. data that is read from this bit reflects the value of the eedo input of the microwire interface. edi/edo has no effect on the eedi pin unless the pread bit is cleared to zero and the een bit is set to one. read accessible always. write accessible only when either the stop or the spnd bit is set. edi/edo is cleared to zero by h_reset and is not affected by s_reset or by setting the stop bit. bcr20: software style bit name description this register is an alias of the lo- cation csr58. accesses to/from this register are equivalent to ac- cesses to csr58. 31C16 res reserved locations. written as zeros and read as undefined. 15C11 res reserved locations. written as zeros and read as undefined. 10 aperren advanced parity error handling enable. when aperren is set to one, the bpe bits (rmd1 and tmd1, bit 23) are used to indi- cated parity error in data transfers to the receive and transmit buffers. note that since the advanced parity error handling uses an additional bit in the descriptor, swstyle (bits 7C0 of this register) must be set to one, two or three to pro- gram the pcnet-pci ii controller to use 32-bitsoftware structures. aperren does not affect the re- porting of address parity errors or data parity errors that occur when the pcnet-pci ii controller is the target of the transfer. read accessible always, write accessible only when either the stop or the spnd bit is set. aperren is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 9 csrpcnet csr pcnet-isa configuration. when set, this bit indicates that the pcnet-pci ii controller regis- ter bits of csr4 and csr3 will map directly to the csr4 and csr3 bits of the pcnet-isa (am79c960) device. when cleared, this bit indicates that pcnet-pci ii controller register bits of csr4 and csr3 will map directly to the csr4 and csr3 bits of the ilacc (am79c900) device. the value of csrpcnet is determined by the pcnet-pci ii controller according to the setting of the software style (swstyle, bits 7C0 of this register). read accessible always. csrpcnet is read only. write operations will be ignored. csrpcnet will be set after h_reset (since swstyle de- faults to zero) and is not affected by s_reset or by set- ting the stop bit. 8 ssize32 32-bit software size. when set, this bit indicates that the amd p r e l i m i n a r y 158 AM79C970A pcnet pci ii controller utilizes 32 bit software structures for the initialization block and the trans mit and receive descriptor en tries. when cleared, this bit indicates that the pcnet pci ii controller utilizes 16 bit software structures for the initialization block and the transmit and receive descriptor entries. in this mode the pcnet pci ii controller is backwards compatible with the am79c90 c lance and am79c960 pcnet isa. the value of ssize32 is deter mined by the pcnet pci ii con troller according to the setting of the software style (swstyle, bits 7-0 of this register). read accessible always. ssize32 is read only. write op erations will be ignored. ssize32 will be cleared after h_reset (since swstyle de faults to zero) and is not af fected by s_reset or by setting the stop bit. if ssize32 is cleared to zero, then bits iadr[31:24] of csr2 will be used to generate values for the upper 8 bits of the 32 bit address bus during master accesses initiated by the pcnet pci ii controller. this ac tion is required, since the 16 bit software structures will yield only 24 bits of address for pcnet pci ii controller bus master accesses. if ssize32 is set to one, then the software structures that are common to the pcnet pci ii controller and the host system will supply a full 32 bits for each address pointer that is needed by the pcnet pci ii controller for performing master accesses. the value of the ssize32 bit has no effect on the drive of the upper 8 address bits. the upper 8 ad dress pins are always driven, re gardless of the state of the ssize32 bit. note that the setting of the ssize32 bit has no effect on the width for i/o accesses. i/o access width is determined by the state of the dwio bit (bcr18, bit 7). 7-0 swstyle software style register. the value in this register determines the style of register and memory resources that shall be used by the pcnet pci ii controller. the software style selection will affect the interpretation of a few bits within the csr space, the or der of the descriptor entries and the width of the descriptors and initialization block entries. all pcnet pci ii controller csr bits and bcr bits and all descriptor, buffer and initializa tion block entries not cited in the table above are unaffected by the software style selection. table 35. software styles swstyle initialization descriptor altered bit [7:0] style name csrpcnet ssize32 block entries ring entries interpretations 00h c lance 1 0 16 bit software 16 bit software all bits in csr4 are / structures, non burst structures, non burst used, tmd1[29] is pcnet isa or burst access access only add_fcs 01h ilacc 0 1 32 bit software 32 bit software csr4[9:8],csr4[5:4] structures, non burst structures, non burst and csr4[1:0] have or burst access access only no function, tmd1[29] is no_fcs. 02h pcnet pci 1 1 32 bit software 32 bit software all bits in csr4 are structures, non burst structures, non burst used, tmd1[29] is or burst access access only add_fcs 03h pcnet pci ii 1 1 32 bit software 32 bit software all bits in csr4 are controller structures, non burst structures, non burst used, tmd1[29] is or burst access or burst access add_fcs all other undefined undefined undefined undefined undefined undefined p r e l i m i n a r y amd 159 AM79C970A read/write accessible only when either the stop or the spnd bit is set. the swstyle register will contain the value 00h following h_reset and will be unaffected by s_reset or by setting the stop bit. bcr21: interrupt control bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 intcon reserved locations. the setting of this register has no effect on any pcnet pci ii controller func tion. it is only included for software compatibility with other pcnet family devices. read/write accessible always. intcon is not affected by s_reset or by setting the stop bit. bcr22: pci latency register bit name description note that bits 15-0 in this register are programmable through the external eeprom. 31-16 res reserved locations. written as zeros and read as undefined. 15-8 max_lat maximum latency. specifies the maximum arbitration latency the pcnet pci ii controller can sus tain without causing problems to the network activity. the register value specifies the time in units of 1/4 microseconds. max_lat is aliased to the pci configuration space register max_lat (offset 3fh). the host should use the value in this register to determine the setting of the pci latency timer register. read accessible always. write accessible only when either the stop or the spnd bit is set. max_lat is set to the value of ffh by h_reset which corresponds to a maximum la tency of 63.75 microseconds. the actual maximum latency the pcnet pci ii controller can han dle is 153.6 m s which is also the value for the bus time out (see csr100). max_lat is not af fected by s_reset or by setting the stop bit. 7-0 min_gnt minimum grant. specifies the minimum length of a burst period the pcnet pci ii controller needs to keep up with the network activ ity. the length of the burst period is calculated assuming a clock rate of 33 mhz. the register value specifies the time in units of 1/4 microseconds. min_gnt is aliased to the pci configuration space register min_gnt (offset 3eh). the host should use the value in this register to determine the setting of the pci latency timer register. read accessible always. write accessible only when either the stop or the spnd bit is set. min_gnt is set to the value of 06h by h_reset which corre sponds to a minimum grant of 1.5 microseconds. 1.5 microseconds is the time it takes to pcnet pci ii controller to read/write 64 bytes. (16 dword transfers in burst mode with one extra wait state per data phase inserted by the target.) note that the default is only a typical value. it also does not take into account any de scriptor accesses. min_gnt is not affected by s_reset or by setting the stop bit. initialization block when ssize32 (bcr20, bit 8) is set to zero, the soft ware structures are defined to be 16 bits wide. the base address of the initialization block must be aligned to a dword boundary, i.e. csr1, bit 1 and 0 must be cleared to zero. when ssize32 is set to zero, the initializa tion block looks like this: amd p r e l i m i n a r y 160 AM79C970A table 36. initialization block (ssize32 = 0) address bits 15-13 bit 12 bits 11-8 bits 7-4 bits 3-0 iadr+00h mode 15-00 iadr+02h padr 15-00 iadr+04h padr 31-16 iadr+06h padr 47-32 iadr+08h ladrf 15-00 iadr+0ah ladrf 31-16 iadr+0ch ladrf 47-32 iadr+0eh ladrf 63-48 iadr+10h rdra 15-00 iadr+12h rlen 0 res rdra 23-16 iadr+14h tdra 15-00 iadr+16h tlen 0 res tdra 23-16 table 37. initialization block (ssize32 = 1) bits bits bits bits bits bits bits bits address 31-28 27-24 23-20 19-16 15-12 11-8 7-4 3-0 iadr+00h tlen res rlen res mode iadr+04h padr 31-00 iadr+08h res padr 47-32 iadr+0ch ladr 31-00 iadr+10h ladr 63-32 iadr+14h rdra 31-00 iadr+18h tdra 31-00 note that the pcnet pci ii controller performs dword accesses to read the initialization block. this statement is always true, regardless of the setting of the ssize32 bit. when ssize32 (bcr20, bit 8) is set to one, the soft ware structures are defined to be 32 bits wide. the base address of the initialization block must be aligned to a dword boundary, i.e. csr1, bits 1 and 0 must be cleared to zero. when ssize32 is set to one, the initialization block looks as shown in table 37. rlen and tlen when ssize32 (bcr20, bit 8) is set to zero, the soft ware structures are defined to be 16 bits wide, and the rlen and tlen fields in the initialization block are each 3 bits wide. the values in these fields determine the number of transmit and receive descriptor ring entries (dre) which are used in the descriptor rings. their meaning is as follows: table 38. r/tlen decoding (ssize32 = 0) r/tlen no. of dres 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 if a value other than those listed in the above table is de sired, csr76 and csr78 can be written after initializa tion is complete. when ssize32 (bcr20, bit 8) is set to one, the soft ware structures are defined to be 32 bits wide, and the rlen and tlen fields in the initialization block are each p r e l i m i n a r y amd 161 AM79C970A 4 bits wide. the values in these fields determine the number of transmit and receive descriptor ring entries (dre) which are used in the descriptor rings. their meaning is as follows: table 39. r/tlen decoding (ssize32 = 1) r/tlen no. of dres 0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 1001 512 11xx 512 1x1x 512 if a value other than those listed in the above table is de sired, csr76 and csr78 can be written after initializa tion is complete. rdra and tdra tdra and rdra indicate where the transmit and re ceive descriptor rings begin. each dre must be located at a16 byte address boundary when ssize32 is set to one (bcr20, bit 8). each dre must be located at an 8 byte address boundary when ssize32 is set to zero (bcr20, bit 8). ladrf the logical address filter (ladrf) is a 64 bit mask that is used to accept incoming logical addresses. if the first bit in the incoming address (as transmitted on the wire) is a one, it indicates a logical address. if the first bit is a zero, it is a physical address and is compared against the physical address that was loaded through the initialization block. 4 1 crc gen sel 31 26 mux 63 0 64 match = 1 packet accepted match = 0 packet rejected match logical address filter (ladrf) 0 6 32-bit resultant crc 1 0 received message destination address 19436a 48 figure 2. address match logic amd p r e l i m i n a r y 162 AM79C970A a logical address is passed through the crc generator, producing a 32 bit result. the high order 6 bits of the crc is used to select one of the 64 bit positions in the logical address filter. if the selected filter bit is set, the address is accepted and the frame is placed into memory. the logical address filter is used in multicast address ing schemes. the acceptance of the incoming frame based on the filter value indicates that the message may be intended for the node. it is the node's responsibility to determine if the message is actually intended for the node by comparing the destination address of the stored message with a list of acceptable logical addresses. if the logical address filter is loaded with all zeros and promiscuous mode is disabled, all incoming logical addresses except broadcast will be rejected. padr this 48 bit value represents the unique node address assigned by the iso 8802 3 (ieee/ansi 802.3) and used for internal address comparison. padr[0] is com pared with the first bit in the destination address of the incoming frame. it must be zero since only the destina tion address of a unicast frames is compared to padr. the six hex digit nomenclature used by the iso 8802 3 (ieee/ansi 802.3) maps to the pcnet pci ii controller padr register as follows: the first byte is compared with padr[7:0], with padr[0] being the least significant bit of the byte. the second iso 8802 3 (ieee/ansi 802.3) byte is compared with padr[15:8], again from the least significant bit to the most significant bit, and so on. the sixth byte is compared with padr[47:40], the least sig nificant bit being padr[40]. mode the mode register field of the initialization block is cop ied into csr15 and interpreted according to the descrip tion of csr15. receive descriptors when swstyle (bcr20, bits 7-0) is set to zero, then the software structures are defined to be 16 bits wide, and receive descriptors, (crda = current receive descriptor address), are as shown in table 40. when swstyle (bcr 20, bits 7-0) is set to one or two, then the software structures are defined to be 32 bits wide, and receive descriptors, (crda = current receive descriptor address), are as shown in table 41. when swstyle (bcr 20, bits 7-0) is set to three, then the software structures are defined to be 32 bits wide, and receive descriptors, (crda = current re ceive descriptor address), are as shown in table 42. table 40. receive descriptor (swstyle = 0) address 15 14 13 12 11 10 9 8 7-0 crda+00h rbadr[15:0] crda+02h own err fram oflo crc buff stp enp rbadr[23:16] crda+04h 1 1 1 1 bcnt crda+06h 0 0 0 0 mcnt table 41. receive descriptor (swstyle = 1,2) address 31 30 29 28 27 26 25 24 23 22 21 20 19-16 15-12 11-0 crda+00h rbadr[31:0] crda+04h own err fram oflo crc buff stp enp bpe pam lafm bam res 1111 bcnt crda+08h rcc rpc 0000 mcnt crda+0ch reserved table 42. receive descriptor (swstyle = 3) address 31 30 29 28 27 26 25 24 23 22 21 20 19-16 15-12 11-0 crda+00h rcc rpc 0000 mcnt crda+04h own err fram oflo crc buff stp enp bpe pam lafm bam res 1111 bcnt crda+08h rbadr[31:0] crda+0ch reserved p r e l i m i n a r y amd 163 AM79C970A rmd0 bit name description 31-0 rbadr receive buffer address. this field contains the address of the receive buffer that is associated with this descriptor. rmd1 bit name description 31 own this bit indicates whether the descriptor entry is owned by the host (own = 0) or by the pcnet pci ii controller (own = 1). the pcnet pci ii controller clears the own bit af ter filling the buffer that the de scriptor points to. the host sets the own bit after emptying the buffer. once the pcnet pci ii controller or host has relin quished ownership of a buffer, it must not change any field in the descriptor entry. 30 err err is the or of fram, oflo, crc, buff or bpe. err is set by the pcnet pci ii controller and cleared by the host. 29 fram framing error indicates that the incoming frame contains a non integer multiple of eight bits and there was an fcs error. if there was no fcs error on the in coming frame, then fram will not be set even if there was a non integer multiple of eight bits in the frame. fram is not valid in internal loopback mode. fram is valid only when enp is set and oflo is not. fram is set by the pcnet pci ii controller and cleared by the host. 28 oflo overflow error indicates that the receiver has lost all or part of the incoming frame, due to an inabil ity to move data from the receive fifo into a memory buffer before the internal fifo overflowed. oflo is valid only when enp is not set. oflo is set by the pcnet pci ii controller and cleared by the host. 27 crc crc indicates that the receiver has detected a crc (fcs) error on the incoming frame. crc is valid only when enp is set and oflo is not. crc is set by the pcnet pci ii controller and cleared by the host. 26 buff buffer error is set any time the pcnet pci ii controller does not own the next buffer while data chaining a received frame. this can occur in either of two ways: 1. the own bit of the next buffer is zero. 2. fifo overflow occurred be fore the pcnet pci ii controller was able to read the own bit of the next descriptor. if a buffer error occurs, an overflow error may also occur in ternally in the fifo, but will not be reported in the descriptor status entry unless both buff and oflo errors occur at the same time. buff is set by the pcnet pci ii controller and cleared by the host. 25 stp start of packet indicates that this is the first buffer used by the pcnet pci ii controller for this frame. if stp and enp are both set to one, the frame fits into a single buffer. otherwise, the frame is spread over more than one buffer. when lappen (csr3, bit 5) is cleared to zero, stp is set by the pcnet pci ii controller and cleared by the host. when lappen is set to one, stp must be set by the host. 24 enp end of packet indicates that this is the last buffer used by the pcnet pci ii controller for this frame. it is used for data chaining buffers. if both stp and enp are set, the frame fits into one buffer and there is no data chaining. enp is set by the pcnet pci ii controller and cleared by the host. 23 bpe bus parity error is set by the pcnet pci ii controller when a parity error occurred on the bus interface during a data transfers to a receive buffer. bpe is valid only when enp, oflo or buff are set. the pcnet pci ii control ler will only set bpe when the ad vanced parity error handling is enabled by setting aperren (bcr20, bit 10) to one. bpe is amd p r e l i m i n a r y 164 AM79C970A set the pcnet pci ii controller and cleared by the host. this bit does not exist, when the pcnet pci ii controller is pro grammed to use 16 bit software structures for the descriptor ring entries (bcr20, bits 7-0, swstyle is cleared to zero). 22 pam physical address match is set by the pcnet pci ii controller when it accepts the received frame due to a match of the frame's destination address with the con tent of the physical address register. pam is valid only when enp is set. pam is set by the pcnet pci ii controller and cleared by the host. this bit does not exist when the pcnet pci ii controller is pro grammed to use 16 bit software structures for the descriptor ring entries (bcr20, bits 7-0, swstyle is cleared to zero). 21 lafm logical address filter match is set by the pcnet pci ii controller when it accepts the received frame based on the value in the logical address filter register. lafm is valid only when enp is set. lafm is set by the pcnet pci ii controller and cleared by the host. note that if drcvbc (csr15, bit 14) is cleared to zero, only bam, but not lafm will be set when a broadcast frame is re ceived, even if the logical ad dress filter is programmed in such a way that a broadcast frame would pass the hash filter. if drcvbc is set to one and the logical address filter is programmed in such a way that a broadcast frame would pass the hash filter, lafm will be set on the reception of a broadcast frame. this bit does not exist when the pcnet pci ii controller is pro grammed to use 16 bit software structures for the descriptor ring entries (bcr20, bits 7-0, swstyle is cleared to zero). 20 bam broadcast address match is set by the pcnet pci ii controller when it accepts the received frame because the frame's desti nation address is of the type broadcast". bam is valid only when enp is set. bam is set by the pcnet pci ii controller and cleared by the host. this bit does not exist when the pcnet pci ii controller is pro grammed to use 16 bit software structures for the descriptor ring entries (bcr20, bits 7-0, swstyle is cleared to zero). 19-16 res reserved locations. these locations should be read and written as zeros. 15-12 ones these four bits must be written as ones. they are written by the host and unchanged by the pcnet pci ii controller. 11-00 bcnt buffer byte count is the length of the buffer pointed to by this de scriptor, expressed as the two's complement of the length of the buffer. this field is written by the host and unchanged by the pcnet pci ii controller. rmd2 bit name description 31-24 rcc receive collision count. indi cates the accumulated number of collisions detected on the net work since the last packet was received, excluding collisions that occurred during transmis sions from this node. the pcnet pci ii controller imple mentation of this counter may not be compatible with the ilacc rcc definition. if network statis tics are to be monitored, then csr114 should be used for the purpose of monitoring receive collisions instead of these bits. 23-16 rpc runt packet count. indicates the accumulated number of runts that were addressed to this node since the last time that a receive packet was successfully re ceived and its corresponding rmd2 ring entry was written to by the pcnet pci ii controller. in order to be included in the rpc value, a runt must be long enough to meet the minimum re quirement of the internal address matching logic. the minimum re quirement for a runt to pass the internal address matching mechanism is: 18 bits of valid p r e l i m i n a r y amd 165 AM79C970A preamble plus a valid sfd de tected, followed by 7 bytes of frame data. this requirement is unvarying, regardless of the ad dress matching mechanisms in force at the time of reception. (i.e. physical, logical, broadcast or promiscuous). the pcnet pci ii controller implementation of this counter may not be compatible with the ilacc rpc definition. 15-12 zeros this field is reserved. pcnet pci ii controller will write zeros to these locations. 11-0 mcnt message byte count is the length in bytes of the received message, expressed as an un signed binary integer. mcnt is valid only when err is clear and enp is set. mcnt is written by the pcnet pci ii controller and cleared by the host. rmd3 bit name description 31-0 res reserved locations. transmit descriptors when swstyle (bcr20, bits 7-0) is set to zero, the software structures are defined to be 16 bits wide, and transmit descriptors, (cxda = current transmit de scriptor address), are as shown in table 43. when swstyle (bcr 20, bits 7-0) is set to one or two, the software structures are defined to be 32 bits wide, and transmit descriptors, (cxda = current trans mit descriptor address), are as shown in table 44. when swstyle (bcr 20, bits 7-0) is set to three, then the software structures are defined to be 32 bits wide, and transmit descriptors, (cxda = current trans mit descriptor address), are as shown in table 45. table 43. transmit descriptor (swstyle = 0) address 15 14 13 12 11 10 9 8 7-0 cxda+00h tbadr[15:0] cxda+02h own err add_/ more one def stp enp tbadr[23:16] no_ / fcs ltint cxda+04h 1 1 1 1 bcnt cxda+06h buff uflo ex lcol lcar rtry tdr def table 44. transmit descriptor (swstyle = 1,2) address 31 30 29 28 27 26 25 24 23 22-16 15-12 11-4 3-0 cxda+00h tbadr[31:0] cxda+04h own err add_/ more one def stp enp bpe res 1111 bcnt no_ / fcs ltint cxda+08h buff uflo ex lcol lcar rtry tdr res trc def cxda+0ch reserved table 45. transmit descriptor (swstyle = 3) address 31 30 29 28 27 26 25 24 23 22-16 15-12 11-4 3-0 cxda+00h buff uflo ex lcol lcar rtry tdr res trc def cxda+04h own err add_/ more one def stp enp bpe res 1111 bcnt no_ / fcs ltint cxda+08h tbadr[31:0] cxda+0ch reserved amd p r e l i m i n a r y 166 AM79C970A tmd0 bit name description 31-0 tbadr transmit buffer address. this field contains the address of the transmit buffer that is associated with this descriptor. tmd1 bit name description 31 own this bit indicates whether the descriptor entry is owned by the host (own = 0) or by the pcnet pci ii controller (own = 1). the host sets the own bit after filling the buffer pointed to by the descriptor entry. the pcnet pci ii controller clears the own bit after transmit ting the contents of the buffer. both the pcnet pci ii controller and the host must not alter a de scriptor entry after it has relin quished ownership. 30 err err is the or of uflo, lcol, lcar, rtry or bpe. err is set by the pcnet pci ii controller and cleared by the host. this bit is set in the current descriptor when the error occurs, and there fore may be set in any descriptor of a chained buffer transmission. 29 add_fcs/no bit 29 functions as when _fcs swstyle (bcr20, bits 7-0) is set to one (ilacc style). otherwise bit 29 functions as add_fcs. add_fcs add_fcs dynamically controls the generation of fcs on a frame by frame basis. it is valid only if the stp bit is set. when add_fcs is set, the state of dxmtfcs is ignored and transmitter fcs generation is activated. when add_fcs is cleared to zero, fcs generation is controlled by dxmtfcs. when apad_xmt (csr4, bit 11) is set to one, the setting of add_fcs has no effect. add_fcs is set by the host, and is not changed by the pcnet pci ii controller. this is a reserved bit in the c lance (am79c90). this function differs from the corre sponding ilacc function. no_fcs no_fcs dynamically controls the generation of fcs on a frame by frame basis. it is valid only if the enp bit is set. when no_fcs is set, the state of dxmtfcs is ignored and trans mitter fcs generation is deacti vated. when no_fcs is cleared to zero, fcs generation is con trolled by dxmtfcs. when apad_xmt (csr4, bit 11) is set to one, the setting of no_fcs has no effect. no_fcs is set by the host, and is not changed by the pcnet pci ii controller. this is a reserved bit in the c lance (am79c90). this function is identical to the corresponding ilacc function. 28 more/ltint bit 28 always function as more. the value of more is written by the pcnet pci ii controller and is read by the host. when ltinten is cleared to zero (csr5, bit 14), the pcnet pci ii controller will never look at the content of bit 28, write operations by the host have no effect. when ltinten is set to one bit 28 changes its function to ltint on host write operations and on pcnet pci ii controller read operations. more more indicates that more than one retry was needed to transmit a frame. the value of more is written by the pcnet pci ii con troller. this bit has meaning only if the enp bit is set. ltint ltint is used to suppress inter rupts after successful transmis sion on selected frames. when ltint is cleared to zero and enp is set to one, the pcnet pci ii controller will not set tint (csr0, bit 9) after a successful transmission. tint will only be set when the last de scriptor of a frame has both ltint and enp set to one. when ltint is cleared to zero, it will only cause the suppression of interrupts for successful trans mission. tint will always be set if the transmission has an error. the ltinten overrides the func tion of tokintd (csr5, bit 15). 27 one one indicates that exactly one retry was needed to transmit a frame. one flag is not valid when p r e l i m i n a r y amd 167 AM79C970A lcol is set. the value of the one bit is written by the pcnet pci ii controller. this bit has meaning only if the enp bit is set. 26 def deferred indicates that the pcnet pci ii controller had to defer while trying to transmit a frame. this condition occurs if the channel is busy when the pcnet pci ii controller is ready to transmit. def is set by the pcnet pci ii controller and cleared by the host. 25 stp start of packet indicates that this is the first buffer to be used by the pcnet pci ii controller for this frame. it is used for data chaining buffers. the stp bit must be set in the first buffer of the frame, or the pcnet pci ii controller will skip over the descriptor and poll the next de scriptor(s) until the own and stp bits are set. stp is set by the host and is not changed by the pcnet pci ii controller. 24 enp end of packet indicates that this is the last buffer to be used by the pcnet pci ii controller for this frame. it is used for data chaining buffers. if both stp and enp are set, the frame fits into one buffer and there is no data chaining. enp is set by the host and is not changed by the pcnet pci ii controller. 23 bpe bus parity error is set by the pcnet pci ii controller when a parity error occurred on the bus interface during a data transfers from the transmit buffer associ ated with this descriptor. the pcnet pci ii controller will only set bpe when the advanced par ity error handling is enabled by setting aperren (bcr20, bit 10) to one. bpe is set by the pcnet pci ii controller and cleared by the host. this bit does not exist, when the pcnet pci ii controller is pro grammed to use 16 bit software structures for the descriptor ring entries (bcr20, bits 7-0, swstyle is cleared to zero). 22-16 res reserved locations. 15-12 ones these four bits must be written as ones. this field is written by the host and unchanged by the pcnet pci ii controller. 11-00 bcnt buffer byte count is the usable length of the buffer pointed to by this descriptor, expressed as the two's complement of the length of the buffer. this is the number of bytes from this buffer that will be transmitted by the pcnet pci ii controller. this field is written by the host and is not changed by the pcnet pci ii controller. there are no minimum buffer size restrictions. tmd2 bit name description 31 buff buffer error is set by the pcnet pci ii controller during transmission when the pcnet pci ii controller does not find the enp flag in the current descriptor and does not own the next descriptor. this can occur in either of two ways: 1. the own bit of the next de scriptor is zero. 2. fifo underflow occurred be fore the pcnet pci ii con troller obtained the status byte (tmd1[31:24]) of the next descriptor. buff is set by the pcnet pci ii controller and cleared by the host. if a buffer error occurs, an un derflow error will also occur. buff is not valid when lcol or rtry error is set during transmit data chaining. buff is set by the pcnet pci ii controller and cleared by the host. 30 uflo underflow error indicates that the transmitter has truncated a mes sage because it could not read data from memory fast enough. uflo indicates that the fifo has emptied before the end of the frame was reached. when dxsuflo (csr3, bit 6) is cleared to zero, the transmitter is turned off when an uflo error occurs (csr0, txon = 0). when dxsuflo is set to one, the pcnet pci ii controller gracefully recovers from an uflo error. it scans the transmit descriptor ring until it finds the amd p r e l i m i n a r y 168 AM79C970A start of a new frame and starts a new transmission. uflo is set by the pcnet pci ii controller and cleared by the host. 29 exdef excessive deferral. indicates that the transmitter has experi enced excessive deferral on this transmit frame, where excessive deferral is defined in iso 8802 3 (ieee/ansi 802.3). excessive deferral will also set the interrupt bit exdint (csr5, bit 7). 28 lcol late collision indicates that a collision has occurred after the first slot time of the channel has elapsed. the pcnet pci ii con troller does not retry on late collisions. lcol is set by the pcnet pci ii controller and cleared by the host. 27 lcar loss of carrier is set when the carrier is lost during a pcnet pci ii controller initiated transmission when in aui or gpsi mode and the device is op erating in half duplex mode. the pcnet pci ii controller does not retry upon loss of carrier. it will continue to transmit the whole frame until done. lcar will not be set when the device is operat ing in full duplex mode and the aui or gpsi port is active. lcar is not valid in internal loopback mode. lcar is set by the pcnet pci ii controller and cleared by the host. in 10base t mode, lcar will be set when the t mau was in link fail state during the transmission. 26 rtry retry error indicates that the transmitter has failed after 16 at tempts to successfully transmit a message, due to repeated colli sions on the medium. if drty is set to one in the mode register, rtry will set after 1 failed trans mission attempt. rtry is set by the pcnet pci ii controller and cleared by the host. 25-16 tdr time domain reflectometer re flects the state of an internal pcnet pci ii controller counter that counts at a 10 mhz rate from the start of a transmission to the occurrence of a collision or loss of carrier. this value is useful in determining the approximate distance to a cable fault. the tdr value is written by the pcnet pci ii controller and is valid only if rtry is set. note that 10 mhz gives very low resolution and in general has not been found to be particularly useful. this feature is here primarily to maintain full compatibility with the c lance device (am79c90). 15-4 res reserved locations. 3-0 trc transmit retry count. indicates the number of transmit retries of the associated packet. the maximum count is 15. however, if a retry error occurs, the count will roll over to zero. in this case only, the transmit retry count value of zero should be interpreted as meaning 16. trc is written by the pcnet pci ii controller into the last transmit descriptor of a frame, or when an error terminates a frame. valid only when own is cleared to zero. tmd3 bit name description 31-0 res reserved locations. p r e l i m i n a r y amd 169 AM79C970A register summary pci configuration registers offset name width in bit access mode default value 00h pci vendor id 16 ro 1022h 02h pci device id 16 ro 2000h 04h pci command 16 rw 0000h 06h pci status 16 rw 0280h 08h pci revision id 8 ro 1xh 09h pci programming if 8 ro 00h 0ah pci sub class 8 ro 00h 0bh pci base class 8 ro 02h 0ch reserved 8 ro 00h 0dh pci latency timer 8 ro 00h 0eh pci header type 8 ro 00h 0fh reserved 8 ro 00h 10h pci i/o base address 32 rw 0000 0001h 14h pci memory mapped i/o 32 rw 0000 0000h base address 18h-2fh reserved 8 ro 00h 30h pci expansion rom 8 ro 0000 0000h base address 34-3bhh reserved 8 ro 00h 3ch pci interrupt line 8 rw 00h 3dh pci interrupt pin 8 ro 01h 3eh pci min_gnt 8 ro 06h 3fh pci max_lat 8 ro ffh 40h-ffh reserved 8 ro 00h note: ro = read only, rw = read/write, x = silicon revision dependent amd p r e l i m i n a r y 170 AM79C970A control and status registers rap addr symbol default value comments use 00 csr0 uuuu 0004 pcnet pci ii controller status register r 01 csr1 uuuu uuuu lower iadr]: maps to location 16 s 02 csr2 uuuu uuuu upper iadr: maps to location 17 s 03 csr3 uuuu 0000 interrupt masks and deferral control s 04 csr4 uuuu 0115 test and features control r 05 csr5 uuuu 0000 extended control and interrupt r 06 csr6 uuuu uuuu rxtx: rx/tx encoded ring lengths s 07 csr7 uuuu uuuu reserved 08 csr8 uuuu uuuu ladr0: logical address filter ladrf[15:0] s 09 csr9 uuuu uuuu ladr1: logical address filter ladrf[31:16] s 10 csr10 uuuu uuuu ladr2: logical address filter ladrf[47:32] s 11 csr11 uuuu uuuu ladr3: logical address filter ladrf[63:48] s 12 csr12 uuuu uuuu padr0: physical address register padr[15:0][ s 13 csr13 uuuu uuuu padr1: physical address register padr[31:16] s 14 csr14 uuuu uuuu padr2: physical address register padr[47:32] s 15 csr15 see reg. desc. mode: mode register s 16 csr16 uuuu uuuu iadr[15:0]: base address of init block lower (copy) t 17 csr17 uuuu uuuu iadr[31:16]: base address of init block upper (copy) t 18 csr18 uuuu uuuu crbal: current receive buffer address lower t 19 csr22 uuuu uuuu crbau: current receive buffer address upper t 20 csr20 uuuu uuuu cxbal: current transmit buffer address lower t 21 csr21 uuuu uuuu cxbau: current transmit buffer address upper t 22 csr22 uuuu uuuu nrbal: next receive buffer address lower t 23 csr23 uuuu uuuu nrbau: next receive buffer address upper t 24 csr24 uuuu uuuu badrl: base address of receive ring lower s 25 csr25 uuuu uuuu badru: base address of receive ring upper s 26 csr26 uuuu uuuu nrdal: next receive descriptor address lower t 27 csr27 uuuu uuuu nrdau: next receive descriptor address upper t 28 csr28 uuuu uuuu crdal: current receive descriptor address lower t 29 csr29 uuuu uuuu crdau: current receive descriptor address upper t 30 csr30 uuuu uuuu badxl: base address of transmit descriptor ring lower s 31 csr31 uuuu uuuu badxu: base address of transmit descriptor ring upper s 32 csr32 uuuu uuuu nxdal: next xmt descriptor address lower t 33 csr33 uuuu uuuu nxdau: next xmt descriptor address upper t 34 csr34 uuuu uuuu cxdal: current transmit descriptor address lower t 35 csr35 uuuu uuuu cxdau: current transmit descriptor address upper t 36 csr36 uuuu uuuu nnrdal: next next receive descriptor address lower t 37 csr37 uuuu uuuu nnrdau: next next receive descriptor address upper t note: u = undefined value, r = running register, s = setup register, t = test register p r e l i m i n a r y amd 171 AM79C970A control and status registers (continued) rap addr symbol default value comments use 38 csr38 uuuu uuuu nnxdal: next next transmit descriptor address lower t 39 csr39 uuuu uuuu nnxdau: next next transmit descriptor address upper t 40 csr40 uuuu uuuu crbc: current receive byte count t 41 csr41 uuuu uuuu crst: current receive status t 42 csr42 uuuu uuuu cxbc: current transmit byte count t 43 csr43 uuuu uuuu cxst: current transmit status t 44 csr44 uuuu uuuu nrbc: next receive byte count t 45 csr45 uuuu uuuu nrst: next receive status t 46 csr46 uuuu uuuu poll: poll time counter t 47 csr47 uuuu uuuu pi: polling interval s 48 csr48 uuuu uuuu reserved 49 csr49 uuuu uuuu reserved 50 csr50 uuuu uuuu reserved 51 csr51 uuuu uuuu reserved 52 csr52 uuuu uuuu reserved 53 csr53 uuuu uuuu reserved 54 csr54 uuuu uuuu reserved 55 csr55 uuuu uuuu reserved 56 csr56 uuuu uuuu reserved 57 csr57 uuuu uuuu reserved 58 csr58 see reg. desc. sws: software style s 59 csr59 uuuu uuuu reserved 60 csr60 uuuu uuuu pxdal: previous transmit descriptor address lower t 61 csr61 uuuu uuuu pxdau: previous transmit descriptor address upper t 62 csr62 uuuu uuuu pxbc: previous transmit byte count t 63 csr63 uuuu uuuu pxst: previous transmit status t 64 csr64 uuuu uuuu nxba: next transmit buffer address lower t 65 csr65 uuuu uuuu nxbau: next transmit buffer address upper t 66 csr66 uuuu uuuu nxbc: next transmit byte count t 67 csr67 uuuu uuuu nxst: next transmit status t 68 csr68 uuuu uuuu reserved 69 csr69 uuuu uuuu reserved 70 csr70 uuuu uuuu reserved 71 csr71 uuuu uuuu reserved 72 csr72 uuuu uuuu rcvrc: receive ring counter t 73 csr73 uuuu uuuu reserved 74 csr74 uuuu uuuu xmtrc: transmit descriptor ring counter t 75 csr75 uuuu uuuu reserved 76 csr76 uuuu uuuu rcvrl: receive descriptor ring length s 77 csr77 uuuu uuuu reserved 78 csr78 uuuu uuuu xmtrl: transmit descriptor ring length s 79 csr79 uuuu uuuu reserved 80 csr80 uuuu 1410 dmatcfw: dma transfer counter and fifo watermark s 81 csr81 uuuu uuuu reserved 82 csr82 uuuu 0000 dmabat: bus activity timer s amd p r e l i m i n a r y 172 AM79C970A control and status registers (continued) rap addr symbol default value comments use 83 csr83 uuuu uuuu reserved 84 csr84 uuuu uuuu dmaba: address register lower t 85 csr85 uuuu uuuu dmabau: address register upper t 86 csr86 uuuu uuuu dmabc: buffer byte counter t 87 csr87 uuuu uuuu reserved 88 csr88 0242 1003 chip id register lower t 89 csr89 uuuu 0262 chip id register upper t 90 csr90 uuuu uuuu reserved 91 csr91 uuuu uuuu reserved 92 csr92 uuuu uuuu reserved 93 csr93 uuuu uuuu reserved 94 csr94 uuuu 0000 xmttdr: transmit time domain reflectometry count t 95 csr95 uuuu uuuu reserved 96 csr96 uuuu uuuu reserved 97 csr97 uuuu uuuu reserved 98 csr98 uuuu uuuu reserved 99 csr99 uuuu uuuu reserved 100 csr100 uuuu 0200 bus time out s 101 csr101 uuuu uuuu reserved 102 csr102 uuuu uuuu reserved 103 csr103 uuuu 0105 reserved 104 csr104 uuuu uuuu reserved 105 csr105 uuuu uuuu reserved 106 csr106 uuuu uuuu reserved 107 csr107 uuuu uuuu reserved 108 csr108 uuuu uuuu reserved 109 csr109 uuuu uuuu reserved 110 csr110 uuuu uuuu reserved 111 csr111 uuuu uuuu reserved 112 csr112 uuuu 0000 missed frame count r 113 csr113 uuuu uuuu reserved 114 csr114 uuuu 0000 receive collision count r 115 csr115 uuuu uuuu reserved 116 csr116 uuuu uuuu reserved 117 csr117 uuuu uuuu reserved 118 csr118 uuuu uuuu reserved 119 csr119 uuuu uuuu reserved 120 csr120 uuuu uuuu reserved 121 csr121 uuuu uuuu reserved 122 csr122 uuuu 0000 receive frame alignment control s 123 csr123 uuuu uuuu reserved 124 csr124 uuuu 0000 test register 1 125 csr125 uuuu uuuu reserved 126 csr126 uuuu uuuu reserved 127 csr127 uuuu uuuu reserved t p r e l i m i n a r y amd 173 AM79C970A bus configuration registers bcr mnemonic default description user eeprom 0 msrda 0005h reserved no no 1 mswra 0005h reserved no no 2 mc 0002h miscellaneous configuration yes yes 3 reserved n/a reserved no no 4 lnkst 00c0h link status led yes no 5 led1 0084h led1 status yes no 6 led2 0088h led2 status yes no 7 led3 0090h led3 status yes no 8 reserved n/a reserved no no 9 fdc 0000h full duplex control yes yes 10-15 reserved n/a reserved no no 16 iobasel n/a reserved yes yes 17 iobaseu n/a reserved yes yes 18 bsbc 9001h burst size and bus control yes yes 19 eecas 0002h eeprom control and status yes no 20 sws 0200h software style yes no 21 intcon n/a reserved yes yes 22 pcilat ff06h pci latency yes yes programmability amd p r e l i m i n a r y 174 AM79C970A absolute maximum ratings storage temperature -65 c to +150 c . . . . . . . . . . . ambient temperature under bias -65 c to +125 c . . supply voltage to av ss or v ssb (av dd , v d d , v ddb ) 0.3 v to +6.0 v . . . . . . . . . . . . . . . . . . stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices temperature (t a )0 c to + 70 c . . . . . . . . . . . . . . . . . supply voltages (av dd , v dd ) +5v 5% . . . . . . . . . . . . . . . . . . . . . . . . . (v ddb for 5 v signaling) +5v 5% . . . . . . . . . . . . . . . (v ddb for 3.3 v signaling) + 3.3 v 10% . . . . . . . . . . . all inputs within the range: av ss - 0.5 v v in . . . . . av dd + 0.5 v, or v ss - 0.5 v v in v dd + 0.5 v, or v ssb - 0.5 < v in < v ddb + 0.5v operating ranges define those limits between which the func tionality of the device is guaranteed. dc characteristics over commercial operating ranges unless otherwise specified parameter symbol parameter description test conditions min max units digital input voltage for 5 v signaling v il input low voltage 0.8 v v ih input high voltage 2.0 v digital output voltage for 5 v signaling v ol output low voltage i ol1 = 3 ma 0.45 v i ol2 = 6 ma i ol3 = 12 ma (note 1) v oh output high voltage (note 2) i oh = -2 ma (note 3) 2.4 v digital input leakage current for 5 v signaling i ix input low leakage current (note 4) v in = 0 v, v dd = v ddb = 5 v -10 10 m a digital output leakage current for 5 v signaling i ozl output low leakage current (note 5) v out = 0.4v -10 m a i ozh output high leakage current (note 5) v out = v dd , v ddb 10 m a digital input voltage for 3.3 v signaling v il input low voltage -0.5 0.325 v v ddb v ih input high voltage 0.475 v ddb v v ddb + 0.5 digital output voltage for 3.3 v signaling v ol output low voltage i ol = 1.5 ma 0.1 v ddb v v oh output high voltage (note 2) i oh = -0.5 ma 0.9 v ddb v digital input leakage current for 3.3 v signaling i ix input low leakage current v in = 0 v, v dd = v ddb = 3.3 v -10 10 m a (note 4) digital output leakage current for 3.3 v signaling i ozl output low leakage current (note 5) v out = 0.4v -10 m a i ozh output high leakage current (note 5) v out = v dd , v ddb 10 m a p r e l i m i n a r y amd 175 AM79C970A dc characteristics over commercial operating ranges unless otherwise specified (continued) parameter symbol parameter description test conditions min max units crystal input current v ilx xtal1 input low voltage threshold v in = external clock -0.5 0.8 v v ihx xtal1 input high voltage threshold v in = external clock v dd - 0.8 v dd + 0.5 v i ilx xtal1 input low current v in = external clock active -120 0 m a v in = v ss sleep -10 +10 m a i ihx xtal1 input high current v in = external clock active 0 120 m a v in = vdd sleep 400 m a power supply current i dd active power supply current xtal1 = 20 mhz, 90 ma clk = 33 mhz i ddcoma sleep mode power supply current sleep active 200 m a awake = 0 (bcr2, bit 2) i ddsnooze auto wake mode power supply current sleep active 10 ma awake = 1 (bcr2, bit 2) i ddmagic0 magic packet mode clk = 0 mhz (note 10) 47 ma power supply current i ddmagic33 magic packet mode clk = 33 mhz (note 10) 80 ma power supply current pin capacitance c in input pin capacitance fc = 1 mhz (note 6) 10 pf c idsel idsel pin capacitance fc = 1 mhz (note 6) 8 pf c o i/o or output pin capacitance fc = 1 mhz (note 6) 10 pf c clk clk pin capacitance fc = 1 mhz (note 6) 5 12 pf twisted pair interface (10base t) i irxd input current at rxd av ss < v in < av dd -500 500 m a r rxd rxd differential input resistance 10 k w v tivb rxd+, rxd- open circuit i in = 0 ma av dd -3.0 av dd -1.5 v input voltage (bias) v tidv differential mode input voltage av dd = 5.0 v -3.1 3.1 v range (rxd ) v tsq+ rxd positive squelch threshold (peak) sinusoid 5 mhz f 10 mhz 300 520 mv lrt = 0 (csr15, bit 9) v tsq- rxd negative squelch threshold (peak) sinusoid 5 mhz f 10 mhz -520 -300 mv lrt = 0 (csr15, bit 9) v ths+ rxd post squelch positive sinusoid 5 mhz f 10 mhz threshold (peak) lrt = 0 (csr15, bit 9) 150 293 mv v ths- rxd post squelch negative sinusoid 5 mhz f 10 mhz threshold (peak) lrt = 0 (csr15, bit 9) -293 -150 mv v ltsq+ rxd positive squelch threshold (peak) sinusoid 5 mhz f 10 mhz lrt = 1 (csr15, bit 9) 180 312 mv v ltsq- rxd negative squelch threshold (peak) sinusoid 5 mhz f 10 mhz lrt = 1 (csr15, bit 9) -312 -180 mv v lths+ rxd post squelch positive sinusoid 5 mhz f 10 mhz threshold (peak) lrt = 1 (csr15, bit 9) 90 176 mv v lths- rxd post squelch negative sinusoid 5 mhz f 10 mhz threshold (peak) lrt = 1 (csr15, bit 9) -176 -90 mv amd p r e l i m i n a r y 176 AM79C970A dc characteristics over commercial operating ranges unless otherwise specified (continued) parameter symbol parameter description test conditions min max units twisted pair interface (10base t) (continued) v rxdth rxd switching threshold (note 6) -35 35 mv v txh txd and txp output high voltage av ss = 0 v av dd -0.6 av dd v v txl txd and txp output low voltage av dd = 5 v av ss av ss +0.6 v v txi txd and txp differential output voltage imbalance -40 40 mv v txoff txd and txp idle output voltage 40 mv r tx txd , txp differential driver (note 6) 80 w output impedance attachment unit interface (aui) i iaxd input current at di+ and di- -1v < v in < av dd + 0.5 v -500 +500 m a i iaxc input current at ci+ and ci- -1v < v in < av dd + 0.5 v -500 +500 m a v aod differential output voltage r l = 78 w 630 1200 mv |(do+)-(do-)| v aodoff transmit differential output idle voltage r l = 78 w (note 9) -40 40 mv i aodoff transmit differential output idle current r l = 78 w (note 8) -1 1 ma v cmt transmit output common mode voltage r l = 78 w 2.5 av dd v v odi do transmit differential output r l = 78 w (note 7) 25 mv voltage imbalance v ath receive data differential input threshold -35 35 mv v asq di and ci differential input -275 -160 mv threshold (squelch) v irdvd di and ci differential mode input -1.5 1.5 v voltage range v icm di and ci input bias voltage i in = 0 ma av dd -3.0 av dd -1.0 v v opd do undershoot voltage at zero (note 9) -100 mv differential on transmit return to zero (etd) notes: 1. i ol1 applies to ad[31:0], c/ be [3:0], par and req . i ol2 applies to devsel , frame , inta , irdy , perr , serr , stop , trdy , eecs , era[7:0], eraclk , eroe , dxcvr/ nout, erd7/txdat, erd6/txen and tdo. i ol3 applies to eesk/ led1 /sfbd, led2 /srdclk, eedo/ led3 /srd, and eedi/ lnkst . 2. v oh does not apply to open drain output pins. 3. outputs are cmos and will be driven to rail if the load is not resistive. 4. i ix applies to all input pins except xtal1. 5. i ozl and i ozh apply to all three state output pins and bi directional pins. 6. parameter not tested. value determined by characterization. 7. tested, but to values in excess of limits. test accuracy not sufficient to allow screening guard bands. 8. correlated to other tested parameters not tested directly. 9. test not implemented to data sheet specification. 10. the power supply current in magic packet mode is linear. for example, at clk = 20 mhz the maximum magic packet mode power supply current would be 67 ma. p r e l i m i n a r y amd 177 AM79C970A switching characteristics: bus interface parameter symbol parameter description test conditions min max unit clock timing f clk clk frequency 0 33 mhz t cyc clk period @ 1.5 v for v ddb = 5 v 30 ns @ 0.4 v ddb for v ddb = 3.3 v t high clk high time @ 2.0 v for v ddb = 5 v 12 ns @ 0.475 v ddb for v ddb = 3.3 v t low clk low time @ 0.8 v for v ddb = 5 v 12 ns @ 0.325 v ddb for v ddb = 3.3 v t fall clk fall time over 2 v p p for v ddb = 5 v 1 4 v/ns over 0.4 v ddb p-p for v ddb = 3.3 v (note 1) t rise clk rise time over 2 v p p for v ddb = 5 v 1 4 v/ns over 0.4 v ddb p-p for v ddb = 3.3 v (note 1) output and float delay timing t val ad[31:00], c/ be [3:0], par, @ 1.5 v for v ddb = 5 v 2 11 ns frame , irdy , trdy , stop , @ 0.4 v ddb for v ddb = 3.3 v devsel , perr , serr valid delay t val ( req ) req valid delay @ 1.5 v for v ddb = 5 v 2 12 ns @ 0.4 v ddb for v ddb = 3.3 v t on ad[31:00], c/ be [3:0], par, frame , @ 1.5 v for v ddb = 5 v 2 11 ns irdy , trdy , stop , devsel @ 0.4 v ddb for v ddb = 3.3 v active delay t off ad[31:00], c/ be [3:0], par, frame , @ 1.5 v for v ddb = 5 v 28 ns irdy , trdy , stop , devsel @ 0.4 v ddb for v ddb = 3.3 v float delay setup and hold timing t su ad[31:00], c/ be [3:0], par, frame , @ 1.5 v for v ddb = 5 v 7 ns irdy , trdy , stop , lock , devsel , @ 0.4 v ddb for v ddb = 3.3 v idsel setup time t h ad[31:00], c/ be [3:0], par, frame , @ 1.5 v for v ddb = 5 v 0 ns irdy , trdy , stop , lock , devsel , @ 0.4 v ddb for v ddb = 3.3 v idsel hold time t su ( gnt ) gnt setup time @ 1.5 v for v ddb = 5 v 10 ns @ 0.4 v ddb for v ddb = 3.3 v t h ( gnt ) gnt hold time @ 1.5 v for v ddb = 5 v 0 ns @ 0.4 v ddb for v ddb = 3.3 v amd p r e l i m i n a r y 178 AM79C970A switching characteristics: bus interface (continued) parameter symbol parameter description test conditions min max unit eeprom timing f eesk (eesk) eesk frequency @ 1.5 v for v (note 2) 650 khz t high (eesk) eesk high time @ 0.2 v 780 ns t low eesk low time @ 0.8 v 780 ns t val (eedi) eedi valid output delay from eesk @ 1.5 v for v (note 2) -15 -15 ns t val (eesk) eecs valid output delay from eesk @ 1.5 v for v (note 2) -15 -15 ns t low (eecs) eecs low time @ 1.5 v for v (note 2) 1550 ns t su (eedo) eedo setup time to eesk @ 1.5 v for v (note 2) 50 ns t h (eedo) eedo hold time from eesk @ 1.5 v for v (note 2) 0 ns expansion rom interface timing t val (era) era valid delay from clk @ 1.5 v ns t val (eroe) eroe valid delay from clk @ 1.5 v ns t val eraclk valid delay from clk @ 1.5 v ns (eraclk) t su (erd) erd setup time to clk @ 1.5 v ns t h (erd) erd hold time to clk @ 1.5 v ns jtag (ieee 1149.1) test signal timing t j1 tck frequency 10 mhz t j2 tck period 100 t j3 tck high time @ 2.0 v 45 ns t j4 tck low time @ 0.8 v 45 ns t j5 tck rise time 4ns t j6 tck fall time 4ns t j7 tdi, tms setup time 8 ns t j8 tdi, tms hold time 10 ns t 9 tdo valid delay 3 30 ns t j9 tdo float delay 50 ns t j11 all outputs (non test) valid delay 3 25 ns t j12 all outputs (non test) float delay 36 ns t j13 all outputs (non test) setup time 8 ns t j4 all outputs (non test) hold time 7 ns note: 1. not tested; parameter guaranteed by characterization. 2. parameter value is given for automatic eeprom read operation. when eeprom port (bcr19) is used to access the eeprom, software is responsible for meeting eeprom timing requirements. p r e l i m i n a r y amd 179 AM79C970A switching characteristics: 10base?t interface parameter symbol parameter description test conditions min max unit transmit timing t tetd transmit start of idle 250 350 ns t tr transmitter rise time (10% to 90%) 5.5 ns t tf transmitter fall time (90% to 10%) 5.5 ns t tm transmitter rise and fall time mismatch (t tm = |t tr - t tf |) 1 ns t xmton xmt asserted delay 100 ns t xmtoff xmt deasserted delay 20 62 ms t perlp idle signal period 8 24 ms t pwlp idle link pulse width (note 1) 75 120 ns t pwplp predistortion idle link pulse width (note 1) 45 55 ns t ja transmit jabber activation time 20 150 ms t jr transmit jabber reset time 250 750 ms t jrec transmit jabber recovery time 1.0 m s (minimum time gap between transmitted frames to prevent jabber activation) receiving timing t pwnrd rxd pulse width not to turn off v in > v ths (min) 136 ns internal carrier sense t pwroff rxd pulse width to turn off v in > v ths (min) 200 ns t retd receive start of idle 200 ns t rcvon rcv asserted delay tron tron ns - 50 + 100 t rcvon rcv deasserted delay 20 62 ms collision detection and sqe test t colon col asserted delay 750 900 ns t coloff col deasserted delay 20 62 ms note: 1. not tested; parameter guaranteed by characterization. amd p r e l i m i n a r y 180 AM79C970A switching characteristics: aui parameter symbol parameter description test conditions min max unit aui port t dotr do+, do- rise time (10% to 90%) 2.5 5.0 ns t dotf do+, do- fall time (10% to 90%) 2.5 5.0 ns t dorm do+, do- rise and fall time mismatch 1.0 ns t doetd do end of transmission 200 375 ns t pwodi di pulse width accept/reject threshold |v in | > |vasq| (note 1) 15 45 ns t pwkdi di pulse width maintain/turn off |v in | > |vasq| (note 2) 136 200 ns threshold t pwoci ci pulse width accept/reject threshold |v in | > |vasq| (note 3) 10 26 ns t pwkci ci pulse width maintain/turn off |v in | > |vasq| (note 4) 90 160 ns threshold internal mendec clock timing t x1 xtal1 period v in = external clock 49.995 50.001 ns t x1h xtal1 high pulse width v in = external clock 20 ns t x1l xtal1 low pulse width v in = external clock 20 ns t x1r xtal1 rise time v in = external clock 5 ns t x1f xtal1 fall time v in = external clock 5 ns notes: 1. di pulses narrower than t pwodi (min) will be rejected; pulses wider than t pwodi (max) will turn internal di carrier sense on. 2. di pulses narrower than t pwkdi (min) will maintain internal di carrier sense on; pulses wider than t pwkdi (max) will turn internal di carrier sense off. 3. ci pulses narrower than t pwoci (min) will be rejected; pulses wider than t pwoci (max) will turn internal ci carrier sense on. 4. ci pulses narrower than t pwkci (min) will maintain internal ci carrier sense on; pulses wider than t pwkci (max) will turn internal ci carrier sense off. p r e l i m i n a r y amd 181 AM79C970A switching characteristics: gpsi parameter symbol parameter name test condition min max unit transmit timing t gpt1 txclk period (802.3 compliant) @ 1.5 v 99.99 100.01 ns t gpt2 txclk high time @ 2.0 v 40 60 ns t gpt3 txdat and txen delay from @ 1.5 v 0 70 ns - txclk t gpt4 rxen setup before @ 1.5 v 210 ns - txclk (last bit) t gpt5 rxen hold after txen @ 1.5 v 0 ns t gpt6 clsn active time to trigger collision @ 1.5 v (note 1) 110 ns t gpt7 clsn active to rxen to @ 1.5 v 0 ns prevent lcar assertion t gpt8 clsn active to rxen for @ 1.5 v 0 4.0 m s sqe heartbeat window t gpt9 clsn active to - rxen for @ 1.5 v 15 ns normal collision receive timing t gpr1 rxclk period @ 1.5 v (note 2) 80 120 ns t gpr2 rxclk high time @ 2.0 v (note 2) 30 80 ns t gpr3 rxclk low time @ 0.8 v (note 2) 30 80 ns t gpr4 rxdat and rxen setup to - rxclk @ 1.5 v 15 ns t gpr5 rxdat hold after - rxclk @ 1.5 v 15 ns t gpr6 rxen hold after rxclk @ 1.5 v 0 ns t gpr7 clsn active to first - rxclk @ 1.5 v 0 ns (collision recognition) t gpr8 clsn active to rxclk @ 1.5 v (note 3) 51.2 m s for address type designation bit t gpr9 clsn setup to last - rxclk for @ 1.5 v 210 ns collision recognition t gpr10 clsn active @ 1.5 v 110 ns t gpr11 clsn inactive setup to first - rxclk @ 1.5 v 300 ns t gpr12 clsn inactive hold to last - rxclk @ 1.5 v 300 ns notes: 1. clsn must be asserted for a continuous period of 110 ns or more. assertion for less than 110 ns period may or may not result in clsn recognition. 2. rxclk should meet jitter requirements of ieee 802.3 specification. 3. clsn assertion before 51.2 m s will be indicated as a normal collision. clsn assertion after 51.2 m s will be considered as a late receive collision. amd p r e l i m i n a r y 182 AM79C970A switching characteristics: eadi parameter symbol parameter name test condition min max unit t ead1 srd setup to srdclk @ 1.5 v 40 ns t ead2 srd hold to srdclk @ 1.5 v 40 ns t ead3 sf/bd change to srdclk @ 1.5 v C15 +15 ns t ead4 ear deassertion to srdclk (first rising edge) @ 1.5 v 50 ns t ead5 ear assertion after sfd event (frame rejection) @ 1.5 v 200 51,090 ns t ead6 ear assertion @ 1.5 v 110 ns p r e l i m i n a r y amd 183 AM79C970A key to switching waveforms must be steady may change from h to l may change from l to h does not apply don't care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high impedance off" state waveform inputs outputs ks000010 switching test circuits c l v threshold i ol i oh sense point 19436a 49 normal and tri state outputs amd p r e l i m i n a r y 184 AM79C970A switching test circuits av dd do+ 154 w 100 pf do- av ss 52.3 w test point 19436a 50 aui do switching test circuit dv dd txd+ 294 w 100 pf txd- dv ss 294 w test point includes test jig capacitance 19436a 51 txd switching test circuit dv dd txp+ 715 w 100 pf txp- dv ss 715 w test point includes test jig capacitance 19436a 52 txp outputs test circuit p r e l i m i n a r y amd 185 AM79C970A switching waveforms: system bus interface clk t high t fall t cyc t rise t low 2.0 v 1.5 v 0.8 v 0.4v 2.0 v 1.5 v 0.8 v 2.4 v 19436a 53 clk waveform for 5 v signaling clk t high t fall t cyc t rise t low 0.475 v ddb 0.4 v ddb 0.325 v ddb 0.2 v ddb 0.475 v ddb 0.4 v ddb 0.325 v ddb 0.6 v ddb 19436a 54 clk waveform for 3.3 v signaling clk t h ad[31:00], c/ be [3:0], par, frame , irdy , trdy , stop , lock , devsel , idsel t su gnt t h( gnt ) t su( gnt ) tx tx 19436a 55 input setup and hold timing amd p r e l i m i n a r y 186 AM79C970A switching waveforms: system bus interface clk t val( req ) tx tx tx min max valid n valid n+1 req min max valid n valid n+1 t val ad[31:00] c/ be [3:0], par, frame , irdy , trdy , stop , devsel , perr , serr fig 55 19436a 56 output valid delay timing clk tx tx tx ad[31:00], c/ be [3:0], par, frame , irdy , trdy , stop , devsel, perr ad[31:00], c/ be [3:0], par, frame , irdy , trdy , stop , devsel, perr valid n t off t on valid n 19436a 57 output tri state delay timing eecs eesk eedi eedo 01 10 a5 a4 a3 a2 a1 a0 d15 d14 d13 d2 d1 d0 19436a 58 automatic eeprom read functional timing p r e l i m i n a r y amd 187 AM79C970A switching waveforms: system bus interface eesk eedo stable eedi eecs t high (eesk) t low (eesk) t low (eecs) t su (eedo) t h (eedo) t val (eedi,eecs) 19436a 59 automatic eeprom read timing clk tx tx tx min max valid n valid n+1 era eroe min max valid n valid n+1 t val (eraclk) eraclk min max valid n valid n+1 t val ( eroe ) erd t val (era) t h (erd) t su (erd) 19436a 60 expansion rom read timing amd p r e l i m i n a r y 188 AM79C970A switching waveforms: system bus interface tck t j3 t j6 t j2 t j5 t j4 2.0 v 1.5 v 0.8 v 2.0 v 1.5 v 0.8 v 19436a 61 jtag (ieee 1149.1) tck waveform for 5 v signaling tck tdi, tms tdo t j8 output signals t j2 t j7 t j9 t j11 t j14 input signals t j12 t j13 19436a 62 jtag (ieee 1149.1) test signal timing p r e l i m i n a r y amd 189 AM79C970A switching waveforms: 10base t interface 19436a 63 t xmtoff txp+ txd txp txd+ t tetd t tf xmt t10bttx t tr t xmton transmit timing txd+ txp+ txd- txp- t pwlp t perl t pwplp 19436a 64 idle link test pulse amd p r e l i m i n a r y 190 AM79C970A switching waveforms: 10base t interface rxd v ltsq v ltsq+ v lths v lths + 19436a 65 receive thresholds (lrt = 1) rxd v tsq- v tsq+ v ths- v ths + 19436a 66 receive thresholds (lrt = 0) p r e l i m i n a r y amd 191 AM79C970A switching waveforms: aui t xi t dotr t dotf t x1h t x1l t x1f t x1r 1 1 0 1 xtal1 istdclk (note 1) itxdat+ (note 1) do+ do- do 0 1 1 itxen (note 1) 19436a 67 note 1: internal signal and is shown for clarification only. transmit timing start of packet typical > 200 ns t doetd xtal1 istdclk (note 1) itxen (note 1) itxdat+ (note 1) do+ do- do 0 1 0 0 10 bit (n-2) bit (n-1) bit (n) 1 19436a 68 note 1: internal signal and is shown for clarification only. transmit timing end of packet (last bit = 0) amd p r e l i m i n a r y 192 AM79C970A switching waveforms: aui typical > 250 ns t doetd xtal1 itxen (note 1) itxdat+ (note 1) do+ do- do 0 11 0 1 bit (n-2) bit (n-1) bit (n) 1 istdclk (note 1) 19436a 69 note 1: internal signal and is shown for clarification only. transmit timing end of packet (last bit = 1) p r e l i m i n a r y amd 193 AM79C970A switching waveforms: aui di+/- v asq t pwodi t pwkdi t pwkdi 19436a 70 receive timing diagram ci+/- v asq t pwoci t pwkci t pwkci 19436a 71 collision timing diagram t doetd do+/- 40 mv 100 mv max. 0 v 80 bit times 19436a 72 port do etd waveform amd p r e l i m i n a r y 194 AM79C970A switching waveforms: gpsi transmit clock (stdclk) transmit data (txdat) transmit enable (txen) carrier present (rxcrs) (note 1) collision (clsn) (note 2) (first bit preamble) t gpt1 t gpt2 t gpt3 t gpt3 t gpt3 t gpt7 t gpt8 t gpt9 t gpt6 t gpt5 (last bit) notes: 1. if rxcrs is not present during transmission, lcar bit in tmd2 will be set. 2. if clsn is not present during or shortly after transmission, cerr in csr0 will be set. t gpt4 19436a 73 transmit timing receive clock (srdclk) (first bit preamble) (address type designation bit) (last bit) t gpr1 t gpr2 t gpr3 t gpr4 t gpr5 t gpr5 t gpr6 t gpr7 t gpr8 t gpr9 t gpr10 t gpr11 t gpr12 (no collision) receive data (rxdat) carrier present (rxcrs) collision (clsn), active collision (clsn), inactive t gpr4 19436a 74 receive timing p r e l i m i n a r y amd 195 AM79C970A switching waveforms: eadi ear srdclk srd sf/bd t ead4 t ead1 t ead2 one zero one sfd bit 0 bit 1 bit 2 bit 3 bit 4 bit 8 bit 0 bit 7 bit 8 t ead3 t ead3 t ead5 t ead6 preamble data field reject accept 19436a-75 eadi reject timing amd p r e l i m i n a r y 196 AM79C970A physical dimensions* pqb132 plastic quad flat pack, trimmed and formed (measured in inches) pin 132 pin 99 pin 66 pin 1 i.d. 16-038-pqb pqb132 db87 7-26-94 ae top view 1.097 1.103 0.947 0.953 1.075 1.085 1.097 1.103 0.008 0.012 pin 33 1.075 1.085 0.947 0.953 0.025 basic 0.160 0.180 0.80 ref bottom view 0.130 0.150 0.020 0.040 seating plane *for reference only. bsc is an ansi standard for basic space centering. trademarks copyright ? 1995 advanced micro devices, inc. all rights reserved. amd and the amd logo are registered trademarks of advanced micro devices, inc. embedded erase and embedded program are trademarks of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies. p r e l i m i n a r y amd 197 AM79C970A physical dimensions pqb132 molded carrier ring plastic quad flat pack (measured in inches, ring measured in millimeters) 16-0000038-pqb-1 pqb132 (molded) da84 6-14-94 ae 45.87 46.13 45.50 45.90 41.37 41.63 37.87 38.13 35.15 35.25 32.15 32.25 1.097 1.103 .944 .952 .944 .952 1.097 1.103 32.15 32.25 35.15 35.25 37.87 38.13 41.37 41.63 45.50 45.90 45.87 46.13 .750 nom. pin 132 pin 1 4.80 2.00 256 nom. side view 1.50 dia. 1.80 pin 99 pin 66 z1 1.50 dia. pin 33 z2 1.50 dia. amd p r e l i m i n a r y 198 AM79C970A physical dimensions pdl144 thin quad flat pack (measured in inches, ring measured in millimeters) 1.00 ref. 1.60 max 11 ?13 11 ?13 0.50 bsc 144 1 1.35 1.45 21.80 22.20 19.80 20.20 21.80 22.20 19.80 20.20 0.17 0.27 16-038-pqt-1_ak pdl144 6-17-96 lv a 1 AM79C970A pcnet pci ii compatible media interface modules appendix a pcnet pci ii compatible 10base t filters and transformers the table below provides a sample list of pcnet pci ii compatible 10base t filter and transformer modules available from various vendors. contact the respective manufacturer for a complete and updated listing of components. filters filters filters filters transformers and transformers transformers resistors manufacturer part no. package transformers and choke dual chokes dual chokes bel fuse a556 2006 de 16 pin 0.3 dil ? bel fuse 0556 2006 00 14 pin sip ? bel fuse 0556 2006 01 14 pin sip ? bel fuse 0556 6392 00 16 pin 0.5 dil ? halo electronics fd02 101g 16 pin 0.3 dil ? halo electronics fd12 101g 16 pin 0.3 dil ? halo electronics fd22 101g 16 pin 0.3 dil ? pca electronics epa1990a 16 pin 0.3 dil ? pca electronics epa2013d 16 pin 0.3 dil ? pca electronics epa2162 16 pin 0.3 sip ? pulse engineering pe 65421 16 pin 0.3 dil ? pulse engineering pe 65434 16 pin 0.3 sil ? pulse engineering pe 65445 16 pin 0.3 dil ? pulse engineering pe 65467 12 pin 0.5 smt ? valor electronics pt3877 16 pin 0.3 dil ? valor electronics fl1043 16 pin 0.3 dil ? amd a 2 AM79C970A pcnet pci ii compatible aui isolation transformers the table below provides a sample list of pcnet pci ii compatible aui isolation transformers available from various vendors. contact the respective manufacturer for a complete and updated listing of components. manufacturer part no. package description bel fuse a553 0506 ab 16 pin 0.3 dil 50 m h bel fuse s553 0756 ae 16 pin 0.3 smd 75 m h halo electronics td01 0756k 16 pin 0.3 dil 75 m h halo electronics tg01 0756w 16 pin 0.3 smd 75 m h pca electronics ep9531 4 16 pin 0.3 dil 50 m h pulse engineering pe64106 16 pin 0.3 dil 50 m h pulse engineering pe65723 16 pin 0.3 smt 75 m h valor electronics lt6032 16 pin 0.3 dil 75 m h valor electronics st7032 16 pin 0.3 smd 75 m h pcnet pci ii compatible dc/dc converters the table below provides a sample list of pcnet pci ii compatible dc/dc converters available from various vendors. contact the respective manufacturer for a complete and updated listing of components. manufacturer part no. package voltage remote on/off halo electronics dcu0 0509d 24 pin dip 5/ 9 no halo electronics dcu0 0509e 24 pin dip 5/ 9 yes pca electronics epc1007p 24 pin dip 5/ 9 no pca electronics epc1054p 24 pin dip 5/ 9 yes pca electronics epc1078 24 pin dip 5/ 9 yes valor electronics pm7202 24 pin dip 5/ 9 no valor electronics pm7222 24 pin dip 5/ 9 yes amd a 3 AM79C970A manufacturer contact information contact the following companies for further informa tion on their products. company u.s. and domestic asia europe bel fuse phone: (201) 432 0463 852 328 5515 33 1 69410402 fax: (201) 432 9542 852 352 3706 33 1 69413320 halo electronics phone: (415) 969 7313 65 285 1566 fax: (415) 367 7158 65 284 9466 pca electronics phone: (818) 892 0761 852 553 0165 33 1 44894800 (hpc in hong kong) fax: (818) 894 5791 852 873 1550 33 1 42051579 pulse engineering phone: (619) 674 8100 852 425 1651 353 093 24107 fax: (619) 675 8262 852 480 5974 353 093 24459 valor electronics phone: (619) 537 2500 852 513 8210 49 89 6923122 fax: (619) 537 2525 852 513 8214 49 89 6926542 b?1 AM79C970A recommendation for power and ground decoupling appendix b the mixed analog/digital circuitry in the pcnet pci ii make it imperative to provide noise free power and ground connections to the device. without clean power and ground connections, a design may suffer from high bit error rates or may not function at all. hence, it is highly recommended that the guidelines presented here are followed to ensure a reliable design. decoupling/bypass capacitors: adequate decoupling of the power and ground pins and planes is required by all pcnet pci ii designs. this includes both low fre quency bulk capacitors and high frequency capacitors. it is recommended that at least one low frequency bulk (e.g. 22 m f) decoupling capacitor be used in the area of the pcnet pci ii device. the bulk capacitor(s) should be connected directly to the power and ground planes. in addition, at least 8 high frequency decoupling capaci tors (e.g. 0.1 m f multilayer ceramic capacitors) should be used around the periphery of the pcnet pci ii device to prevent power and ground bounce from affecting de vice operation. to reduce the inductance between the power and ground pins and the capacitors, the pins should be connected directly to the capacitors, rather than through the planes to the capacitors. the sug gested connection scheme for the capacitors is shown in the figure below. note also that the traces connecting these pins to the capacitors should be as wide as possi ble to reduce inductance (15 mils is desirable). 19436a 57 v dd /v ddb v ss /v ssb c a p pcnet v dd /v ddb v ss /v ssb c a p pcnet c a p pcnet correct correct incorrect via to the power plane via to the ground plane v dd /v ddb v ss /v ssb the most critical pins in the layout of a pcnet pci ii design are the 4 analog power and 2 analog ground pins, avdd[1-4] and avss[1-2], respectively. all of these pins are located in one corner of the device, the analog corner." specific functions and layout requirements of the analog power and ground pins are given below. avss1 and avdd3: these pins provide the power and ground for the twisted pair and aui drivers. in addition avss1 serves as the ground for the logic interfaces in the 20 mhz crystal oscillator. hence, these pins can be very noisy. a dedicated 0.1 m f capacitor between these pins is recommended. avss2 and avdd2: these pins are the most critical pins on the pcnet pci ii device because they provide the power and ground for the phase lock loop (pll) por tion of the chip. the voltage controlled oscillator (vco) portion of the pll is sensitive to noise in the 60 khz - 200 khz. range. to prevent noise in this frequency range from disrupting the vco, it is strongly recommended that the low pass filter shown below be implemented on these pins. amd b 2 AM79C970A 19436a 58 avdd2 avss2 v dd plane v ss plane 33 m f to 10 m f 1 w to 10 w pcnet pci ii 0.1 m f to determine the value for the resistor and capacitor, the formula is: r * c 3 88 where r is in ohms and c is in microfarads. some pos sible combinations are given below. to minimize the voltage drop across the resistor, the r value should not be more than 10 w . 2.7 w 33 m f 4.3 w 22 m f 6.8 w 15 m f 10 w 10 m f rc avss2 and avdd2/avdd4: these pins provide power and ground for the aui and twisted pair receive circuitry. in addition, as mentioned earlier, avss2 and avdd2 provide power and ground for the phase lock loop por tion of the chip. except for the filter circuit already mentioned, no specific decoupling is necessary on these pins. avdd1: avdd1 provides power for the control and in terface logic in the pll. ground for this logic is provided by digital ground pins. no specific decoupling is neces sary on this pin. special note for adapter cards: in adapter card de signs, it is important to utilize all available power and ground pins available on the bus edge connector . in addition, the connection from the bus edge connector to the power or ground plane should be made through more than one via and with wide traces (15 mils desir able) wherever possible. following these recommenda tions results in minimal inductance in the power and ground paths. by minimizing this inductance, ground bounce is minimized. see also the pcnet family board design and layout recommendations applications note (pid# 19595) for additional information. c 1 AM79C970A alternative method for initialization appendix c the pcnet pci ii controller may be initialized by per forming i/o writes only. that is, data can be written di rectly to the appropriate control and status registers (csr instead of reading from the initialization block in memory). the registers that must be written are shown in the table below. these register writes are followed by writing the start bit in csr0. control and status register comment csr2 iadr[31:16]* csr8 ladrf[15:0] csr9 ladrf[31:16] csr10 ladrf[47:32] csr11 ladrf[63:48] csr12 padr[15:0] csr13 padr[31:16] csr14 padr[47:32] csr15 mode csr24 25 badr csr30 31 badx csr47 pollint csr76 rcvrl csr78 xmtrl note : 1. the init bit must not be set or the initialization block will be accessed instead. * needed only if ssize32 = 0. d 1 AM79C970A look ahead packet processing (lapp) concept appendix d introduction of the lapp concept a driver for the pcnet pci ii controller would normally require that the cpu copy receive frame data from the controllers buffer space to the applications buffer space after the entire frame has been received by the control ler. for applications that use a ping pong windowing style, the traffic on the network will be halted until the current frame has been completely processed by the entire application stack. this means that the time be tween last byte of a receive frame arriving at the clients ethernet controller and the clients transmission of the first byte of the next outgoing frame will be separated by: 1. the time that it takes the clients cpus interrupt procedure to pass software control from the cur rent task to the driver 2. plus the time that it takes the client driver to pass the header data to the application and request an application buffer 3. plus the time that it takes the application to gener ate the buffer pointer and then return the buffer pointer to the driver 4. plus the time that it takes the client driver to trans fer all of the frame data from the controllers buffer space into the applications buffer space and then call the application again to process the complete frame 5. plus the time that it takes the application to proc ess the frame and generate the next outgoing frame 6. plus the time that it takes the client driver to set up the descriptor for the controller and then write a tdmd bit to csr0 the sum of these times can often be about the same as the time taken to actually transmit the frames on the wire, thereby yielding a network utilization rate of less than 50%. an important thing to note is that the pcnet pci ii con trollers data transfers to its buffer space are such that the system bus is needed by the pcnet pci ii controller for approximately 4% of the time. this leaves 96% of the system bus bandwidth for the cpu to perform some of the inter frame operations in advance of the completion of network receive activity, if possible. the question then becomes: how much of the tasks that need to be performed between reception of a frame and transmis sion of the next frame can be performed before the re ception of the frame actually ends at the network, and how can the cpu be instructed to perform these tasks during the network reception time? the answer depends upon exactly what is happening in the driver and application code, but the steps that can be performed at the same time as the receive data are ar riving include as much as the first 3 steps and part of the 4 th step shown in the sequence above. by performing these steps before the entire frame has arrived, the frame throughput can be substantially increased. a good increase in performance can be expected when the first 3 steps are performed before the end of the net work receive operation. a much more significant per formance increase could be realized if the pcnet pci ii controller could place the frame data directly into the ap plications buffer space; (i.e., eliminate the need for step 4.) in order to make this work, it is necessary that the ap plication buffer pointer be determined before the frame has completely arrived, then the buffer pointer in the next descriptor for the receive frame would need to be modified in order to direct the pcnet pci ii controller to write directly to the application buffer. more details on this operation will be given later. an alternative modification to the existing system can gain a smaller, but still significant improvement in per formance. this alternative leaves step 4 unchanged in that the cpu is still required to perform the copy opera tion, but it allows a large portion of the copy operation to be done before the frame has been completely received by the controller; i.e., the cpu can perform the copy op eration of the receive data from the pcnet pci ii control lers buffer space into the application buffer space before the frame data has completely arrived from the network. this allows the copy operation of step 4 to be performed concurrently with the arrival of network data, rather than sequentially, following the end of network receive activity. amd d 2 AM79C970A outline of the lapp flow this section gives a suggested outline for a driver that utilizes the lapp feature of the pcnet pci ii controller. note : the labels in the following text are used as refer ences in the timeline diagram that follows. setup: the driver should set up descriptors in groups of 3, with the own and stp bits of each set of three descriptors to read as follows: 11b, 10b, 00b. an option bit (lappen) exists in csr3, bit position 5; the software should set this bit; when set, the lappen bit directs the pcnet pci ii controller to generate an interrupt when stp has been written to a receive descriptor by the pcnet pci ii controller. flow: the pcnet pci ii controller polls the current receive de scriptor at some point in time before a message arrives. the pcnet pci ii controller determines that this receive buffer is owned by the pcnet pci ii controller and it stores the descriptor information to be used when a message does arrive. n0: frame preamble appears on the wire, followed by sfd and destination address. n1: the 64th byte of frame data arrives from the wire. this causes the pcnet pci ii controller to begin frame data dma operations to the first buffer. c0: when the 64th byte of the message arrives, the pcnet pci ii controller performs a lookahead operation to the next receive descriptor. this descriptor should be owned by the pcnet pci ii controller. c1: the pcnet pci ii controller intermittently requests the bus to transfer frame data to the first buffer as it arrives on the wire. s1: the driver remains idle. c2: when the pcnet pci ii controller has completely filled the first buffer, it writes status to the first descriptor. c3: when the first descriptor for the frame has been written, changing ownership from the pcnet pci ii controller to the cpu, the pcnet pci ii controller will generate an srp interrupt. (this interrupt appears as a rint interrupt in csr0). s1: the srp interrupt causes the cpu to switch tasks to allow the pcnet pci ii controllers driver to run. c4: during the cpu interrupt generated task switch ing, the pcnet pci ii controller is performing a lookahead operation to the third descriptor. at this point in time, the third descriptor is owned by the cpu. note : even though the third buffer is not owned by the pcnet pci ii controller, existing amd ethernet controllers will continue to perform data dma into the buffer space that the controller already owns (i.e., buffer number 2). the controller does not know if buffer space in buffer number 2 will be suf ficient or not, for this frame, but it has no way to tell except by trying to move the entire message into that space. only when the message does not fit will it signal a buffer error condition - there is no need to panic at the point that it discovers that it does not yet own descriptor number 3. s2: the first task of the drivers interrupt service rou tine is to collect the header information from the pcnet pci ii controllers first buffer and pass it to the application. s3: the application will return an application buffer pointer to the driver. the driver will add an offset to the application data buffer pointer, since the pcnet pci ii controller will be placing the first por tion of the message into the first and second buff ers. (the modified application data buffer pointer will only be directly used by the pcnet pci ii con troller when it reaches the third buffer.) the driver will place the modified data buffer pointer into the final descriptor of the group (#3) and will grant ownership of this descriptor to the pcnet pci ii controller. c5: interleaved with s2, s3 and s4 driver activity, the pcnet pci ii controller will write frame data to buffer number 2. s4: the driver will next proceed to copy the contents of the pcnet pci ii controllers first buffer to the be ginning of the application space. this copy will be to the exact (unmodified) buffer pointer that was passed by the application. s5: after copying all of the data from the first buffer into the beginning of the application data buffer, the driver will begin to poll the ownership bit of the second descriptor. the driver is waiting for the pcnet pci ii controller to finish filling the second buffer. c6: at this point, knowing that it had not previously owned the third descriptor, and knowing that the current message has not ended (there is more data in the fifo), the pcnet pci ii controller will make a last ditch lookahead to the final (third) de scriptor. this time, the ownership will be true (i.e. the descriptor belongs to the controller), be cause the driver wrote the application pointer into this descriptor and then changed the ownership to give the descriptor to the pcnet pci ii controller back at s3. note that if steps s1, s2 and s3 have not completed at this time, a buff error will result. amd d 3 AM79C970A c7: after filling the second buffer and performing the last chance lookahead to the next descriptor, the pcnet pci ii controller will write the status and change the ownership bit of descriptor number 2. s6: after the ownership of descriptor number 2 has been changed by the pcnet pci ii controller, the next driver poll of the 2nd descriptor will show ownership granted to the cpu. the driver now copies the data from buffer number 2 into the middle section of the application buffer space. this operation is interleaved with the c7 and c8 operations. c8: the pcnet pci ii controller will perform data dma to the last buffer, whose pointer is pointing to ap plication space. data entering the last buffer will not need the infamous double copy that is required by existing drivers, since it is being placed directly into the application buffer space. n2: the message on the wire ends. s7: when the driver completes the copy of buffer number 2 data to the application buffer space, it begins polling descriptor number 3. c9: when the pcnet pci ii controller has finished all data dma operations, it writes status and changes ownership of descriptor number 3. s8: the driver sees that the ownership of descriptor number 3 has changed, and it calls the application to tell the application that a frame has arrived. s9: the application processes the received frame and generates the next tx frame, placing it into a tx buffer. s10: the driver sets up the tx descriptor for the pcnet pci ii controller. amd d 4 AM79C970A 19436a 57 buffer #1 ethernet controller activity: software activity: buffer #2 buffer #3 s0: driver is idle. c1: controller is performing intermittent bursts of dma to fill data buffer #1. ethernet wire activity: n0: packet preamble, sfd and destination address are arriving. c3: srp interrupt is generated. c5: controller is performing intermittent bursts of dma to fill data buffer #2. s1: interrupt latency. s3: driver writes modified application pointer to descriptor #3. c8: controller is performing intermittent bursts of dma to fill data buffer #3. n1: 64th byte of packet data arrives. s4: driver copies data from buffer #1 to the application buffer. s5: driver polls descriptor #2. s7: driver polls descriptor of buffer #3. s8: driver calls application to tell application that packet has arrived. s6: driver copies data from buffer #2 to the application buffer. c9: controller writes descriptor #3. c0: lookahead to descriptor #2. c2: controller writes descriptor #1. s2: driver call to application to get application buffer pointer. { s9: application processes packet, generates tx packet. s10: driver sets up tx descriptor. packet data arriving c4: lookahead to descriptor #3 ( own ). c6: "last chance" lookahead to descriptor #3 (own). c7: controller writes descriptor #2. } }{ { n2: eom figure d1 . lapp timeline lapp software requirements software needs to set up a receive ring with descriptors formed into groups of 3. the first descriptor of each group should have own = 1 and stp = 1, the second descriptor of each group should have own = 1 and stp = 0. the third descriptor of each group should have own = 0 and stp = 0. the size of the first buffer (as indicated in the first descriptor), should be at least equal to the largest expected header size; however, for maxi mum efficiency of cpu utilization, the first buffer size should be larger than the header size. it should be equal to the expected number of message bytes, minus the time needed for interrupt latency and minus the amd d 5 AM79C970A application call latency, minus the time needed for the driver to write to the third descriptor, minus the time needed for the driver to copy data from buffer #1 to the application buffer space, and minus the time needed for the driver to copy data from buffer #2 to the application buffer space. note that the time needed for the copies performed by the driver depends upon the sizes of the 2nd and 3rd buffers, and that the sizes of the second and third buffers need to be set according to the time needed for the data copy operations! this means that an iterative self adjusting mechanism needs to be placed into the software to determine the correct buffer sizing for optimal operation. fixed values for buffer sizes may be used; in such a case, the lapp method will still pro vide a significant performance increase, but the per formance increase will not be maximized. the following diagram illustrates this setup for a receive ring size of 9: 19436a 58 a = expected message size in bytes s1 = interrupt latency s2 = application call latency s3 = time needed for driver to write to third descriptor s4 = time needed for driver to copy data from buffer #1 to application buffer space s6 = time needed for driver to copy data from buffer #2 to application buffer space note that the times needed for tasks s1, s2, s3, s4, and s6 should be divided by 0.8 microseconds to yield an equivalent number of network byte times before subtracting these quantities from the expected message size a. own = 1 stp = 1 size = a-(s1+s2+s3+s4+s6) descriptor #1 own = 1 stp = 0 size = s1+s2+s3+s4 descriptor #2 own = 0 stp = 0 size = s6 descriptor #3 own = 1 stp = 1 descriptor #4 size = a-(s1+s2+s3+s4+s6) own = 1 descriptor #5 stp = 0 size = s1+s2+s3+s4 descriptor #6 own = 0 stp = 0 size = s6 own = 1 stp = 1 descriptor #7 size = a-(s1+s2+s3+s4+s6) own = 1 descriptor #8 stp = 0 size = s1+s2+s3+s4 descriptor #9 own = 0 stp = 0 size = s6 figure d2 . lapp 3 buffer grouping lapp rules for parsing of descriptors when using the lapp method, software must use a modified form of descriptor parsing as follows: software will examine own and stp to determine where a rcv frame begins. rcv frames will only begin in buffers that have own = 0 and stp = 1. software shall assume that a frame continues until it finds either enp = 1 or err= 1. software must discard all descriptors with own = 0 and stp = 0 and move to the next descriptor when searching for the beginning of a new frame; enp and err should be ignored by software during this search. software cannot change an stp value in the re ceive descriptor ring after the initial setup of the ring is complete, even if software has ownership of the stp descriptor unless the previous stp de scriptor in the ring is also owned by the software. when lappen = 1, then hardware will use a modified form of descriptor parsing as follows: the controller will examine own and stp to de termine where to begin placing a rcv frame. a new rcv frame will only begin in a buffer that has own = 1 and stp = 1. the controller will always obey the own bit for determining whether or not it may use the next buffer for a chain. the controller will always mark the end of a frame with either enp = 1 or err= 1. amd d 6 AM79C970A the controller will discard all descriptors with own = 1 and stp = 0 and move to the next de scriptor when searching for a place to begin a new frame. it discards these descriptors by simply changing the ownership bit from own=1 to own = 0. such a descriptor is unused for receive purposes by the controller, and the driver must recognize this. (the driver will recognize this if it follows the software rules). the controller will ignore all descriptors with own = 0 and stp = 0 and move to the next descriptor when searching for a place to begin a new frame. in other words, the controller is al lowed to skip entries in the ring that it does not own, but only when it is looking for a place to begin a new frame. some examples of lapp descriptor interaction choose an expected frame size of 1060 bytes. choose buffer sizes of 800, 200 and 200 bytes. assume that a 1060 byte frame arrives correctly, and that the timing of the early interrupt and the software is smooth. the descriptors will have changed from: own stp enp = own stp enp = (after frame arrival) 1 1 1 x 0 1 0 bytes 1-800 2 1 0 x 0 0 0 bytes 801-1000 3 0 0 x 0 0 1 bytes 1001-1060 4 1 1 x 1 1 x controller's current location 5 1 0 x 1 0 x not yet used 6 0 0 x 0 0 x not yet used etc. 1 1 x 1 1 x not yet used descriptor number before the frame arrives after the frame has arrived comments = enp or err assume that instead of the expected 1060 byte frame, a 900 byte frame arrives, either because there was an error in the network, or because this is the last frame in a file transmission sequence. own stp enp = own stp enp = (after frame arrival) 1 1 1 x 0 1 0 bytes 1-800 2 1 0 x 0 0 1 bytes 801-900 3 0 0 x 0 0 ?* discarded buffer 4 1 1 x 1 1 x controller's current location 5 1 0 x 1 0 x not yet used 6 0 0 x 0 0 x not yet used etc. 1 1 x 1 1 x not yet used descriptor number before the frame arrives after the frame has arrived comments = enp or err amd d 7 AM79C970A note that the pcnet pci ii controller might write a zero to enp location in the 3rd descriptor. here are the two possibilities: 1. if the controller finishes the data transfers into buffer number 2 after the driver writes the applica tions modified buffer pointer into the third descrip tor, then the controller will write a zero to enp for this buffer and will write a zero to own and stp. 2. if the controller finishes the data transfers into buffer number 2 before the driver writes the appli cations modified buffer pointer into the third de scriptor, then the controller will complete the frame in buffer number two and then skip the then un owned third buffer. in this case, the pcnet pci ii controller will not have had the opportunity to reset the enp bit in this descriptor, and it is pos sible that the software left this bit as enp=1 from the last time through the ring. therefore, the soft ware must treat the location as a don't care; the rule is, after finding enp=1 (or err=1) in descrip tor number 2, the software must ignore enp bits until it finds the next stp=1. assume that instead of the expected 1060 byte frame, a 100 byte frame arrives, because there was an error in the network, or because this is the last frame in a file transmission sequence, or per haps because it is an acknowledge frame. * same as note in case 2 above, except that in this case, it is very unlikely that the driver can respond to the inter rupt and get the pointer from the application before the pcnet pci ii controller has completed its poll of the next descriptors. this means that for almost all occurrences of this case, the pcnet pci ii controller will not find the own bit set for this descriptor and therefore, the enp bit will almost always contain the old value, since the pcnet pci ii controller will not have had an opportunity to modify it. ** note that even though the pcnet pci ii controller will write a zero to this enp location, the software should treat the location as a don't care, since after finding the enp=1 in descriptor number 2, the software should ig nore enp bits until it finds the next stp=1. own stp enp = own stp enp = (after frame arrival) 1 1 1 x 0 1 1 bytes 1-100 2 1 0 x 0 0 0** discarded buffer 3 0 0 x 0 0 ?* discarded buffer 4 1 1 x 1 1 x controller's current location 5 1 0 x 1 0 x not yet used 6 0 0 x 0 0 x not yet used etc. 1 1 x 1 1 x not yet used descriptor number before the frame arrives after the frame has arrived comments = enp or err buffer size tuning for maximum performance, buffer sizes should be ad justed depending upon the expected frame size and the values of the interrupt latency and application call la tency. the best driver code will minimize the cpu utili zation while also minimizing the latency from frame end on the network to frame sent to application from driver (frame latency). these objectives are aimed at increasing throughput on the network while decreasing cpu utilization. note that the buffer sizes in the ring may be altered at any time that the cpu has ownership of the correspond ing descriptor. the best choice for buffer sizes will maxi mize the time that the driver is swapped out, while minimizing the time from the last byte written by the pcnet pci ii controller to the time that the data is passed from the driver to the application. in the diagram, this corresponds to maximizing s0, while minimizing the time between c9 and s8. (the timeline happens to show a minimal time from c9 to s8.) note that by increasing the size of buffer number 1, we increase the value of s0. however, when we increase the size of buffer number 1, we also increase the value of s4. if the size of buffer number 1 is too large, then the driver will not have enough time to perform tasks s2, s3, s4, s5 and s6. the result is that there will be delay from the execution of task c9 until the execution of task s8. a perfectly timed system will have the values for s5 and s7 at a minimum. amd d 8 AM79C970A an average increase in performance can be achieved if the general guidelines of buffer sizes in figure 2 is fol lowed. however, as was noted earlier, the correct sizing for buffers will depend upon the expected message size. there are two problems with relating expected message size with the correct buffer sizing: 1. message sizes cannot always be accurately pre dicted, since a single application may expect differ ent message sizes at different times, therefore, the buffer sizes chosen will not always maximize throughput. 2. within a single application, message sizes might be somewhat predictable, but when the same driver is to be shared with multiple applications, there may not be a common predictable message size. additional problems occur when trying to define the cor rect sizing because the correct size also depends upon the interrupt latency, which may vary from system to system, depending upon both the hardware and the software installed in each system. in order to deal with the unpredictable nature of the mes sage size, the driver can implement a self tuning mecha nism that examines the amount of time spent in tasks s5 and s7 as such: while the driver is polling for each de scriptor, it could count the number of poll operations per formed and then adjust the number 1 buffer size to a larger value, by adding t" bytes to the buffer count, if the number of poll operations was greater than x". if fewer than x" poll operations were needed for each of s5 and s7, then the software should adjust the buffer size to a smaller value by, subtracting y" bytes from the buffer count. experiments with such a tuning mechanism must be performed to determine the best values for x" and y". note whenever the size of buffer number 1 is adjusted, buffer sizes for buffer number 2 and buffer 3 should also be adjusted. in some systems, the typical mix of receive frames on a network for a client application consists mostly of large data frames, with very few small frames. in this case, for maximum efficiency of buffer sizing, when a frame ar rives under a certain size limit, the driver should not ad just the buffer sizes in response to the short frame. an alternative lapp flow the two interrupt method an alternative to the above suggested flow is to use two interrupts, one at the start of the receive frame and the other at the end of the receive frame, instead of just look ing for the srp interrupt as was described above. this alternative attempts to reduce the amount of time that the software wastes while polling for descriptor own bits. this time would then be available for other cpu tasks. it also minimizes the amount of time the cpu needs for data copying. this savings can be applied to other cpu tasks. the time from the end of frame arrival on the wire to de livery of the frame to the application is labeled as frame latency. for the one interrupt method, frame latency is minimized, while cpu utilization increases. for the two interrupt method, frame latency becomes greater, while cpu utilization decreases. note that some of the cpu time that can be applied to non ethernet tasks is used for task switching in the cpu. one task switch is required to swap a non ether net task into the cpu (after s7a) and a second task switch is needed to swap the ethernet driver back in again (at s8a). if the time needed to perform these task switches exceeds the time saved by not polling descrip tors, then there is a net loss in performance with this method. therefore, the lapp method implemented should be carefully chosen. amd d 9 AM79C970A figure d3 shows the event flow for the two interrupt method: 19436a 59 buffer #1 ethernet controller activity: software activity: buffer #2 buffer #3 s0: driver is idle. c1: controller is performing intermittent bursts of dma to fill data buffer #1. ethernet wire activity: n0: packet preamble, sfd and destination address are arriving. c3: srp interrupt is generated. c5: controller is performing intermittent bursts of dma to fill data buffer #2. s1: interrupt latency. s3: driver writes modified application pointer to descriptor #3. c8: controller is performing intermittent bursts of dma to fill data buffer #3. n1: 64th byte of packet data arrives. s4: driver copies data from buffer #1 to the application buffer. s5: driver polls descriptor #2. s7: driver is swapped out, allowing a non-etherenet application to run. s8: driver calls application to tell application that packet has arrived. s6: driver copies data from buffer #2 to the application buffer. c9: controller writes descriptor #3. c0: lookahead to descriptor #2. c2: controller writes descriptor #1. s2: driver call to application to get application buffer pointer. { s9: application processes packet, generates tx packet. s10: driver sets up tx descriptor. packet data arriving c4: lookahead to descriptor #3 ( own ). c6: "last chance" lookahead to descriptor #3 (own). c7: controller writes descriptor #2. } }{ { n2: eom c10: erp interrupt is generated. } s8a: interrupt latency. s7a: driver interrupt service routine executes return. { figure d3 . lapp timeline for two interrupt method amd d 10 AM79C970A figure d4 shows the buffer sizing for the two interrupt method. note that the second buffer size will be about the same for each method. 19436a 60 a = expected message size in bytes s1 = interrupt latency s2 = application call latency s3 = time needed for driver to write to third descriptor s4 = time needed for driver to copy data from buffer #1 to application buffer space s6 = time needed for driver to copy data from buffer #2 to application buffer space note that the times needed for tasks s1, s2, s3, s4, and s6 should be divided by 0.8 microseconds to yield an equivalent number of network byte times before subtracting these quantities from the expected message size a. own = 1 stp = 1 size = header_size (minimum 64 bytes) descriptor #1 own = 1 stp = 0 size = s1+s2+s3+s4 descriptor #2 own = 0 stp = 0 size = 1518 - (s1+s2+s3+s4+header_size) descriptor #3 own = 1 stp = 1 descriptor #4 size = header_size (minimum 64 bytes) own = 1 descriptor #5 stp = 0 size = s1+s2+s3+s4 descriptor #6 own = 0 stp = 0 size = 1518 - (s1+s2+s3+s4+header_size) own = 1 stp = 1 descriptor #7 size = header_size (minimum 64 bytes) own = 1 descriptor #8 stp = 0 size = s1+s2+s3+s4 descriptor #9 own = 0 stp = 0 size = 1518 - (s1+s2+s3+s4+header_size) figure d4. lapp 3 buffer grouping for two interrupt method there is another alternative which is a marriage of the two previous methods. this third possibility would use the buffer sizes set by the two interrupt method, but would use the polling method of determining frame end. this will give good frame latency but at the price of very high cpu utilization. and still, there are even more compromise positions that use various fixed buffer sizes and effectively, the flow of the one interrupt method. all of these compromises will reduce the complexity of the one interrupt method by removing the heuristic buffer sizing code, but they all become less efficient than heuristic code would allow. e 1 AM79C970A pcnet pci ii and pcnet pci differences appendix e overview this appendix summarizes the enhancements of the pcnet pci ii controller over the pcnet pci controller. the feature summary is followed by a detailed list of all register bit changes. the document also compares the pinout of the pcnet pci ii controller with the pinout of the pcnet pci and pcnet scsi (also known as golden gate) to show that the flex i/o footprint is continued to be supported. new features n three volt support for pci bus interface n full duplex ethernet n 272 byte transmit fifo, 256 byte receive fifo n enhanced pci bus transfer cycles: no more address stepping initialization block read in non burst (default) or burst mode added new software style and reordered the descriptor entries to allow burst transfers for both, descriptor read and write accesses fifo dma bursts length programmable from 1 to indefinite type of memory command for burst read trans fers programmable to be either memory read line or memory read multiple (controlled by memcmd, bcr18, bit 9) support for fast back to back slave transactions even when the first transaction is addressing a different target memcmd, bcr18, bit 9) enhanced disconnect of i/o burst access n allows i/o resources to be memory mapped n eight bit programmable pci latency timer. min_gnt and max_lat programmable via eeprom n system interrupt for data parity error, master abort or target abort in master cycles n network activity is terminated in an orderly se quence after a master or target abort n advanced parity error handling. mode has enable bit and status bit in rmd1 and tmd1. all network activity is terminated in an orderly sequence. will only work with 32 bit software structures. n all registers in the pci configuration space are cleared by h_reset n expansion rom interface supporting devices of up to 64 k x 8. one external address latch is required. n reading from the s_reset port returns trdy right away n req deassertion programmable to adapt to the requirements of some embedded systems n inta pin programmable for pulse mode to adapt to the requirements of some embedded systems n some previously reserved locations in the eeprom map are now used for new features n suspend mode for graceful stop and access to the csr without reinitialization n user interrupt n reduced number of transmit interrupts: transmit ok disable (csr5, bit 15). when bit is set to one, a transmit interrupt is only gener ated on frames that suffer an error. last transmit interrupt. tmd1, bit 28 is read by the pcnet pci ii controller to determine if an interrupt should be generated at the end of the frame. only interrupts for successful transmis sion can be suppressed. enabled by ltinten (csr5, bit 14). n disable transmit stop on underflow (csr3, bit 6) bit. pcnet pci controller recovers automatically from transmit underflow. n interrupt indication when coming out of sleep mode n interrupt indication for excessive deferral n address match information in receive descriptor n asserting sleep shuts down the entire device n s_reset (reading the reset register) does not affect the tmau, except for the t mau in snooze mode n led registers programmable via eeprom. n magic packet mode n eadi interface. multiplexed with the same led pins as for the pcnet 32. n gpsi interface. multiplexed with the expansion rom interface. use of the expansion rom first, then configuring the pins to the gpsi mode is supported. n jtag interface n fourth led supported amd e 2 AM79C970A n pin to disable external transceiver or dc to dc converter. polarity of assertion state programmable. list of register bit changes pci configuration space command register n adstep (bit 7) now hardwired to zero. was hardwired to one. n memen (bit 1) now read/write accessible. was hardwired to zero. status register n perr (bit 15) now cleared by h_reset. was not effected by h_reset. n serr (bit 14) now cleared by h_reset. was not effected by h_reset. n rmabort (bit 13) now cleared by h_reset. was not effected by h_reset. n rtabort (bit 12) now cleared by h_reset. was not effected by h_reset. n stabort (bit 11) now cleared by h_reset. was not effected by h_reset. n dataperr (bit 8) now cleared by h_reset. was not effected by h_reset. n fbtbc (bit 7) now hardwired to one. was hard wired to zero. revision id register n this 8 bit register is now hardwired to 1xh. it was hardwired to 0xh. latency timer register n this 8 bit register is now read/write accessible. was hardwired to zero. i/o base address register n iobase (bits 31-5) now cleared by h_reset. was not effected by h_reset. memory mapped i/o base address register n new 32 bit register. was reserved, read as zero, writes have no effect. expansion rom base address register n new 32 bit register. was reserved, read as zero, writes have no effect. interrupt line register n this 8 bit register is now cleared by h_reset. was not effected by h_reset. min_gnt register n new 8 bit register. was reserved, read as zero, writes have no effect. max_lat register n new 8 bit register. was reserved, read as zero, writeshave no effect. control and status registers csr0: pcnet pci ii controller control and status register n in addition to the existing interrupt flags, intr (bit 7), the interrupt summary bit, is also affected by the new interrupt flags excessive deferral interrupt (exdint), magic packet interrupt (mpint) sleep interrupt (slpint), system interrupt (sint) and user interrupt (uint). csr3: interrupt masks and deferral control n new bit: dxsuflo (bit 6), disable transmit stop on underflow error. was reserved location, read and written as zero. csr4: test and features control n new bit: uintcmd (bit 7), user interrupt com mand. was reserved location, read and written as zero. n new bit: uint (bit 6), user interrupt. was reserved location, read as zero, written as one or zero. csr5: n new bit: tokintd (bit 15), transmit ok interrupt disable. was reserved location, read and written as zero. n new bit: ltinten (bit 14), last transmit interrupt enable. was reserved location, read and written as zero. n new bit: sint (bit 11), system interrupt. was re served location, read and written as zero. n new bit: sinte (bit 10), system interrupt enable. was reserved location, read and written as zero. n new bit: slpint (bit 9), sleep interrupt. was re served location, read and written as zero. n new bit: slpinte (bit 8), sleep interrupt enable. was reserved location, read and written as zero. n new bit: exdint (bit 7), excessive deferral inter rupt. was reserved location, read and written as zero. n new bit: exdinte (bit 6), excessive deferral inter rupt enable. was reserved location, read and writ ten as zero. n new bit: mpplba (bit 5), magic packet physical logical broadcast accept. was reserved location, read and written as zero. n new bit: mpint (bit 4), magic packet interrupt. was reserved location, read and written as zero. n new bit: mpinte (bit 3), magic packet interrupt enable. was reserved location, read and written as zero. n new bit: mpen (bit 2), magic packet enable. was reserved location, read and written as zero. amd e 3 AM79C970A n new bit: mpmode (bit 1), magic packet mode. was reserved location, read and written as zero. n new bit: spnd (bit 0), suspend. was reserved location, read and written as zero. csr15: mode n portsel (bits 8-7), network port select. new option, value of 10b selects gpsi mode. csr58: software style n new bit: aperren (bit 10), advanced parity error handling enable. was reserved location, read and written as zero. n swstyle (bits 7-0), software style. new option, value of three selects new pcnet pci controller style that reorders 32 bit descriptor entries to allow burst accesses. csr80: dma transfer counter and fifo threshold control n rcvfw (bits 13-12), receive fifo watermark. decoding adjusted for the larger fifo size. n xmtsp (bits 11-10), transmit start point. decod ing adjusted for the larger fifo size. n xmtfw (bits 9-8), transmit fifo watermark. de coding adjusted for the larger fifo size. n dmatc (bits 7-0), dma transfer count. function of the counter is optimized for the pci bus environment. csr82: bus activity timer n dmabat (bits 15-0), dma bus activity timer. function of the counter is optimized for the pci bus environment. csr88: chip id lower n new value: 1003h. was 0003h. csr89: chip id upper n new value : 0262h. was 0243h. csr100: bus timeout n default value now 0600h (153.6 m s) to adjust to the larger fifo size. default value was 0200h (51.2 m s). csr112: missed frame count n counter is stopped while the device is in suspend mode bus configuration registers bcr2: miscellaneous configuration n new bit: intlevel (bit 7), interrupt level. was reserved location, read and written as zero. n new bit: dxcvrctl (bit 5), dxcvr control. was reserved location, read and written as zero. n new bit: dxcvrpol (bit 4), dxcvr polarity. was reserved location, read and written as zero. n new bit: eadisel (bit 3), eadi select. was re served location, read and written as zero. bcr4: link status led n register is now programmable through the eeprom n new bit: mpse (bit 9), magic packet status en able. was reserved location, read and written as zero. n new bit: fdlse (bit 8), full duplex link status enable. was reserved location, read and written as zero. n cole (bit 0), collision status enable. corrected behavior of function. led will not light up due to sqe test collision signal. bcr5: led1 status n register is now programmable through the eeprom n new bit: mpse (bit 9), magic packet status en able. was reserved location, read and written as zero. n new bit: fdlse (bit 8), full duplex link status enable. was reserved location, read and written as zero. n cole (bit 0), collision status enable. corrected behavior of function. led will not light up due to sqe test collision signal. bcr6: led2 status n new register. was reserved location, the settings of the register have no effect on the operation of the device. bcr7: led3 status n register is now programmable through the eeprom n new bit: mpse (bit 9), magic packet status en able. was reserved location, read and written as zero. n new bit: fdlse (bit 8), full duplex link status enable. was reserved location, read and written as zero. n cole (bit 0), collision status enable. corrected behavior of function. led will not light up due to sqe test collision signal. bcr9: full duplex control n new register. was reserved location, read and written as zero. bcr16: i/o base address lower n this register is no longer programmable through the eeprom. the register is reserved and has no effect on the operation of the device. it is only used in the pcnet 32. amd e 4 AM79C970A bcr17: i/o base address upper n this register is no longer programmable through the eeprom. the register is reserved and has no effect on the operation of the device. it is only used in the pcnet 32. bcr18: burst size and bus control n new bits: romtmg (bits 15-12), expansion rom timing. was reserved location, read and written as zero. n new bit: memcmd (bit 9), memory command. was reserved location, read and written as zero. n new bit: extreq (bit 8), extended request. was reserved location, read and written as one. n breade (bit 6), burst read enable. extended functionality of bit. besides enabling burst read accesses to the transmit buffer, breade will now also enable burst read accesses to the initialization block and, if swstyle = 3, to the descriptor ring entries. n bwrite (bit 5), burst write enable. extended functionality of bit. besides enabling burst write accesses to the receive buffer, bwrite will now also enable burst write accesses to the descriptor ring entries, if swstyle = 3. n linbc (bits 2-0), linear burst count. these bits are now reserved and have no effect on the opera tion of the device. bcr20: software style n new bit: aperren (bit 10), advanced parity error handling enable. was reserved location, read and written as zero. n swstyle (bits 7-0), software style. new option, value of three selects new pcnet pci controller style that reorders 32 bit descriptor entries to allow burst accesses. bcr21: interrupt control n this register is no longer programmable through the eeprom. the register is reserved and has no effect on the operation of the device. it is only used in the pcnet 32. bcr22: pci latency n new register. was reserved location, read and written as zero. receive descriptor rmd1 n new bit: bpe (bit 23), bus parity error. this bit is active only if 32 bit software structures are used for the descriptor ring entries (swstyle = one, two or three) and if aperren (bcr20, bit 10) is set to one. was reserved location, read and written as zero. n new bit: pam (bit 22), physical address match. this bit is active only if 32 bit software structures are used for the descriptor ring entries (swstyle = one, two or three). was reserved location, read and written as zero. n new bit: lafm (bit 21), logical address filter match. this bit is active only if 32 bit software structures are used for the descriptor ring entries (swstyle = one, two or three). was re served location, read and written as zero. n new bit: bam (bit 20), broadcast address match. this bit is active only if 32 bit software struc tures are used for the descriptor ring entries (swstyle = one, two or three). was re served location, read and written as zero. transmit descriptor tmd1 n new bit: ltint (bit 28), last transmit interrupt. this bit is only active, if ltinten (csr5, bit 14) is set to one. this bit location is shared with the more status bit. the host will write the bit as ltint and read it as more. the p2 will read the bit as ltint and write it as more. n new bit: bpe (bit 23), bus parity error. this bit is only active, if 32 bit software structures are used for the descriptor ring entries (swstyle = one, two or three) and if aperren (bcr20, bit 10) is set to one. was reserved location, read and written as zero. amd e 5 AM79C970A list of pin changes pin no. pcnet scsi pcnet pci pcnet pci ii comment 9 idsela nc tdi cin must be 8 pf maximum. (pci spec. on idsel input). 58 pwdn nc ear inputs only, ear is ignored until eadi interface is enabled. 60 scsiclk nc eroe external scsi components must be depopulated. 62 busy /nout nout dxcvr/nout external scsi components must be depopulated. 64 scsi bsy nc eraclk external scsi components must be depopulated. 65 scsi atn nc era7 external scsi components must be depopulated. 66 scsi rst nc era6 external scsi components must be depopulated. 68 scsi ds nc era5 external scsi components must be depopulated. 69 scsi sd1 nc era4 external scsi components must be depopulated. 70 scsi sd2 nc era3 external scsi components must be depopulated. 71 scsi sd3 nc era2 external scsi components must be depopulated. 73 scsi sd4 nc era1 external scsi components must be depopulated. 74 scsi sd5 nc era0 external scsi components must be depopulated. 75 scsi sd6 nc erd7/txdat external scsi components must be depopulated. 77 scsi sd7 nc erd6/txen external scsi components must be depopulated. 78 scsi sdp nc erd5 external scsi components must be depopulated. 80 scsi sel nc erd4/txclk external scsi components must be depopulated. 81 scsi req nc erd3/clsn external scsi components must be depopulated. 83 scsi ack nc erd2/rxen external scsi components must be depopulated. 85 scsi msg nc erd1/rxclk external scsi components must be depopulated. 86 scsi c/d nc erd0/rxdat external scsi components must be depopulated. 87 scsi i/o nc led2/srdclk external scsi components must be depopulated. 110 eedo/ led3 eedo/led3 eedo/ led3 /srd eadi interface is only active when enabled by setting a bit in a bcr. 112 eesk/ led1 eesk/led1 eesk/ led1 /sfbd eadi interface is only active when enabled by setting a bit in a bcr. 116 reserved reserved reserved 118 intb nc tck tck is the jtag clock input. the jtag interface is inactive, until tck is running. tck has an internal pull-up. 124 gnta nc tms tms is the jtag test mode select input. tms is only active if tck is running. 127 reqa nc tdo jtag tdo output is tri-state after power-on reset. |
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